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8f9108459e
Based on the support for .req on ARM. The aarch64 variant has to keep track if the alias register was a vector register (v0-31) or a general purpose or VFP/Advanced SIMD ([bhsdq]0-31) register. Patch by Janne Grunau! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212161 91177308-0d34-0410-b5e6-96231b3b80d8
38 lines
1.3 KiB
ArmAsm
38 lines
1.3 KiB
ArmAsm
// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
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bar:
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fred .req x5
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mov fred, x11
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.unreq fred
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fred .req w6
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mov w1, fred
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bob .req fred
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ada .req w1
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mov ada, bob
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.unreq bob
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.unreq fred
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.unreq ada
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// CHECK: mov x5, x11 // encoding: [0xe5,0x03,0x0b,0xaa]
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// CHECK: mov w1, w6 // encoding: [0xe1,0x03,0x06,0x2a]
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// CHECK: mov w1, w6 // encoding: [0xe1,0x03,0x06,0x2a]
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bob .req b6
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hanah .req h5
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sam .req s4
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dora .req d3
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quentin .req q2
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vesna .req v1
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addv bob, v0.8b
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mov hanah, v4.h[3]
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fadd s0, sam, sam
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fmov d2, dora
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ldr quentin, [sp]
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mov v0.8b, vesna.8b
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// CHECK: addv b6, v0.8b // encoding: [0x06,0xb8,0x31,0x0e]
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// CHECK: mov h5, v4.h[3] // encoding: [0x85,0x04,0x0e,0x5e]
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// CHECK: fadd s0, s4, s4 // encoding: [0x80,0x28,0x24,0x1e]
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// CHECK: fmov d2, d3 // encoding: [0x62,0x40,0x60,0x1e]
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// CHECK: ldr q2, [sp] // encoding: [0xe2,0x03,0xc0,0x3d]
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// CHECK: mov v0.8b, v1.8b // encoding: [0x20,0x1c,0xa1,0x0e]
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