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https://github.com/c64scene-ar/llvm-6502.git
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ef5b390263
Fix minimum 16-bit signed value error exposed by MC asm parser tests Add initial MC asm parser tests for the MBlaze backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118844 91177308-0d34-0410-b5e6-96231b3b80d8
254 lines
7.7 KiB
C++
254 lines
7.7 KiB
C++
//===-- MBlazeMCCodeEmitter.cpp - Convert MBlaze code to machine code -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MBlazeMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mblaze-emitter"
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#include "MBlaze.h"
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#include "MBlazeInstrInfo.h"
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#include "MBlazeFixupKinds.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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namespace {
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class MBlazeMCCodeEmitter : public MCCodeEmitter {
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MBlazeMCCodeEmitter(const MBlazeMCCodeEmitter &); // DO NOT IMPLEMENT
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void operator=(const MBlazeMCCodeEmitter &); // DO NOT IMPLEMENT
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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MCContext &Ctx;
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public:
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MBlazeMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
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: TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
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}
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~MBlazeMCCodeEmitter() {}
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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unsigned getBinaryCodeForInstr(const MCInst &MI) const;
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
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unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const {
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return getMachineOpValue(MI, MI.getOperand(OpIdx));
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}
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unsigned getNumFixupKinds() const {
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return 2;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[] = {
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{ "reloc_pcrel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "reloc_pcrel_2byte", 0, 2 * 8, MCFixupKindInfo::FKF_IsPCRel } };
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if (Kind < FirstTargetFixupKind)
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return MCCodeEmitter::getFixupKindInfo(Kind);
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if (unsigned(Kind-FirstTargetFixupKind) < getNumFixupKinds())
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return Infos[Kind - FirstTargetFixupKind];
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assert(0 && "Invalid fixup kind.");
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return Infos[0];
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}
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static unsigned GetMBlazeRegNum(const MCOperand &MO) {
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// FIXME: getMBlazeRegisterNumbering() is sufficient?
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assert(0 && "MBlazeMCCodeEmitter::GetMBlazeRegNum() not yet implemented.");
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return 0;
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}
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void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
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// The MicroBlaze uses a bit reversed format so we need to reverse the
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// order of the bits. Taken from:
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// http://graphics.stanford.edu/~seander/bithacks.html
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C = ((C * 0x80200802ULL) & 0x0884422110ULL) * 0x0101010101ULL >> 32;
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OS << (char)C;
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++CurByte;
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}
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void EmitRawByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
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OS << (char)C;
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++CurByte;
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}
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void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
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raw_ostream &OS) const {
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assert(Size <= 8 && "size too big in emit constant");
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for (unsigned i = 0; i != Size; ++i) {
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EmitByte(Val & 255, CurByte, OS);
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Val >>= 8;
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}
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}
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void EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const;
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void EmitIMM(const MCInst &MI, unsigned op, unsigned &CurByte,
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raw_ostream &OS) const;
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void EmitImmediate(const MCInst &MI,
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unsigned opNo, MCFixupKind FixupKind,
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unsigned &CurByte, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createMBlazeMCCodeEmitter(const Target &,
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TargetMachine &TM,
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MCContext &Ctx) {
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return new MBlazeMCCodeEmitter(TM, Ctx);
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}
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned MBlazeMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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const MCOperand &MO) const {
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if (MO.isReg())
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return MBlazeRegisterInfo::getRegisterNumbering(MO.getReg());
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else if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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else if (MO.isExpr())
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return 0; // The relocation has already been recorded at this point.
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else {
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#ifndef NDEBUG
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errs() << MO;
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#endif
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llvm_unreachable(0);
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}
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return 0;
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}
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void MBlazeMCCodeEmitter::
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EmitIMM(const MCOperand &imm, unsigned &CurByte, raw_ostream &OS) const {
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int32_t val = (int32_t)imm.getImm();
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if (val > 32767 || val < -32768) {
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EmitByte(0x0D, CurByte, OS);
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EmitByte(0x00, CurByte, OS);
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EmitRawByte((val >> 24) & 0xFF, CurByte, OS);
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EmitRawByte((val >> 16) & 0xFF, CurByte, OS);
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}
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}
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void MBlazeMCCodeEmitter::
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EmitIMM(const MCInst &MI, unsigned op, unsigned &CurByte,
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raw_ostream &OS) const {
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MCOperand mcop = MI.getOperand(op);
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if (mcop.isExpr()) {
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EmitByte(0x0D, CurByte, OS);
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EmitByte(0x00, CurByte, OS);
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EmitRawByte(0, CurByte, OS);
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EmitRawByte(0, CurByte, OS);
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}
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}
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void MBlazeMCCodeEmitter::
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EmitImmediate(const MCInst &MI, unsigned opNo, MCFixupKind FixupKind,
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unsigned &CurByte, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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assert(MI.getNumOperands()>opNo && "Not enought operands for instruction");
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MCOperand oper = MI.getOperand(opNo);
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if (oper.isImm()) {
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EmitIMM(oper, CurByte, OS);
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} else if (oper.isExpr()) {
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Fixups.push_back(MCFixup::Create(0,oper.getExpr(),FixupKind));
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}
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}
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void MBlazeMCCodeEmitter::
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EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDesc &Desc = TII.get(Opcode);
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uint64_t TSFlags = Desc.TSFlags;
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// Keep track of the current byte being emitted.
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unsigned CurByte = 0;
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switch ((TSFlags & MBlazeII::FormMask)) {
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default: break;
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case MBlazeII::FPseudo:
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// Pseudo instructions don't get encoded.
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return;
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case MBlazeII::FRRI:
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EmitImmediate(MI, 2, FK_Data_4, CurByte, OS, Fixups);
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break;
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case MBlazeII::FRIR:
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EmitImmediate(MI, 1, FK_Data_4, CurByte, OS, Fixups);
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break;
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case MBlazeII::FCRI:
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EmitImmediate(MI, 1, MCFixupKind(MBlaze::reloc_pcrel_2byte), CurByte, OS,
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Fixups);
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break;
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case MBlazeII::FRCI:
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EmitImmediate(MI, 1, MCFixupKind(MBlaze::reloc_pcrel_4byte), CurByte, OS,
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Fixups);
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case MBlazeII::FCCI:
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EmitImmediate(MI, 0, MCFixupKind(MBlaze::reloc_pcrel_4byte), CurByte, OS,
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Fixups);
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break;
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}
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++MCNumEmitted; // Keep track of the # of mi's emitted
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unsigned Value = getBinaryCodeForInstr(MI);
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switch (Opcode) {
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default:
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EmitConstant(Value, 4, CurByte, OS);
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break;
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case MBlaze::BRLID:
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case MBlaze::BRALID:
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EmitIMM(MI,1,CurByte,OS);
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EmitConstant(Value, 4, CurByte, OS);
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break;
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case MBlaze::BRI:
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case MBlaze::BRAI:
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case MBlaze::BRID:
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case MBlaze::BRAID:
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EmitIMM(MI,0,CurByte,OS);
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EmitConstant(Value, 4, CurByte, OS);
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break;
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}
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}
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// FIXME: These #defines shouldn't be necessary. Instead, tblgen should
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// be able to generate code emitter helpers for either variant, like it
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// does for the AsmWriter.
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#define MBlazeCodeEmitter MBlazeMCCodeEmitter
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#define MachineInstr MCInst
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#include "MBlazeGenCodeEmitter.inc"
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#undef MBlazeCodeEmitter
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#undef MachineInstr
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