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https://github.com/c64scene-ar/llvm-6502.git
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3e59040810
Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163137 91177308-0d34-0410-b5e6-96231b3b80d8
19 lines
424 B
LLVM
19 lines
424 B
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s
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; CHECK: r[[T0:[0-9]+]] = #7
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; CHECK: memw(r29 + #0) = r[[T0]]
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; CHECK: r5 = #6
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; CHECK: r0 = #1
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; CHECK: r1 = #2
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; CHECK: r2 = #3
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; CHECK: r3 = #4
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; CHECK: r4 = #5
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define void @foo() nounwind {
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entry:
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call void @bar(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7)
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ret void
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}
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declare void @bar(i32, i32, i32, i32, i32, i32, i32)
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