Tim Northover 9105f66d6f AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64. ... I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209576 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-24 12:42:26 +00:00
..
AsmParser	AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.	2014-05-24 12:42:26 +00:00
Disassembler	AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.	2014-05-24 12:42:26 +00:00
InstPrinter	ARM64: remove '#' from annotation of add/sub immediate	2014-05-22 14:20:05 +00:00
MCTargetDesc	AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.	2014-05-24 12:42:26 +00:00
TargetInfo	AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.	2014-05-24 12:42:26 +00:00
Utils
ARM64.h
ARM64.td
ARM64AddressTypePromotion.cpp
ARM64AdvSIMDScalarPass.cpp
ARM64AsmPrinter.cpp	AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.	2014-05-24 12:42:26 +00:00
ARM64BranchRelaxation.cpp
ARM64CallingConv.h
ARM64CallingConvention.td
ARM64CleanupLocalDynamicTLSPass.cpp
ARM64CollectLOH.cpp
ARM64ConditionalCompares.cpp
ARM64DeadRegisterDefinitionsPass.cpp
ARM64ExpandPseudoInsts.cpp
ARM64FastISel.cpp
ARM64FrameLowering.cpp	ARM64: model pre/post-indexed operations properly.	2014-05-22 11:56:20 +00:00
ARM64FrameLowering.h
ARM64InstrAtomics.td
ARM64InstrFormats.td	ARM64: model pre/post-indexed operations properly.	2014-05-22 11:56:20 +00:00
ARM64InstrInfo.cpp	ARM64: model pre/post-indexed operations properly.	2014-05-22 11:56:20 +00:00
ARM64InstrInfo.h
ARM64InstrInfo.td	ARM64: these work too	2014-05-22 12:14:49 +00:00
ARM64ISelDAGToDAG.cpp	ARM64: extract a 32-bit subreg when selecting an inreg extend	2014-05-24 07:05:42 +00:00
ARM64ISelLowering.cpp	[ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD with swapped input vectors.	2014-05-23 02:54:50 +00:00
ARM64ISelLowering.h
ARM64LoadStoreOptimizer.cpp	ARM64: model pre/post-indexed operations properly.	2014-05-22 11:56:20 +00:00
ARM64MachineFunctionInfo.h
ARM64MCInstLower.cpp
ARM64MCInstLower.h
ARM64PerfectShuffle.h
ARM64PromoteConstant.cpp
ARM64RegisterInfo.cpp
ARM64RegisterInfo.h
ARM64RegisterInfo.td
ARM64SchedA53.td
ARM64SchedCyclone.td
ARM64Schedule.td
ARM64SelectionDAGInfo.cpp
ARM64SelectionDAGInfo.h
ARM64StorePairSuppress.cpp
ARM64Subtarget.cpp
ARM64Subtarget.h
ARM64TargetMachine.cpp	AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.	2014-05-24 12:42:26 +00:00
ARM64TargetMachine.h
ARM64TargetObjectFile.cpp
ARM64TargetObjectFile.h
ARM64TargetTransformInfo.cpp
CMakeLists.txt
LLVMBuild.txt
Makefile