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Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
2.0 KiB
C++
53 lines
2.0 KiB
C++
//===-- Thumb2RegisterInfo.cpp - Thumb-2 Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-2 implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#include "Thumb2RegisterInfo.h"
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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using namespace llvm;
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Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii,
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const ARMSubtarget &sti)
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: ARMBaseRegisterInfo(tii, sti) {
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}
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void
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Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned SubIdx,
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int Val,
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned MIFlags) const {
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MachineFunction &MF = *MBB.getParent();
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MachineConstantPool *ConstantPool = MF.getConstantPool();
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const Constant *C = ConstantInt::get(
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Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
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unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
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BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
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.addReg(DestReg, getDefRegState(true), SubIdx)
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.addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
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.setMIFlags(MIFlags);
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}
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