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Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
200 lines
7.4 KiB
C++
200 lines
7.4 KiB
C++
//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips16 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips16InstrInfo.h"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MipsMachineFunction.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
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: MipsInstrInfo(tm, Mips::BimmX16),
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RI(*tm.getSubtargetImpl(), *this) {}
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const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
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return RI;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned Mips16InstrInfo::
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned Mips16InstrInfo::
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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return 0;
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}
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void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.contains(DestReg) &&
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Mips::CPURegsRegClass.contains(SrcReg))
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Opc = Mips::MoveR3216;
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else if (Mips::CPURegsRegClass.contains(DestReg) &&
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Mips::CPU16RegsRegClass.contains(SrcReg))
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Opc = Mips::Move32R16;
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else if ((SrcReg == Mips::HI) &&
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(Mips::CPU16RegsRegClass.contains(DestReg)))
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Opc = Mips::Mfhi16, SrcReg = 0;
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else if ((SrcReg == Mips::LO) &&
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(Mips::CPU16RegsRegClass.contains(DestReg)))
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Opc = Mips::Mflo16, SrcReg = 0;
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assert(Opc && "Cannot copy registers");
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
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if (DestReg)
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MIB.addReg(DestReg, RegState::Define);
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if (SrcReg)
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MIB.addReg(SrcReg, getKillRegState(KillSrc));
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}
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void Mips16InstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
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Opc = Mips::SwRxSpImmX16;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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}
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void Mips16InstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
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Opc = Mips::LwRxSpImmX16;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
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.addMemOperand(MMO);
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}
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bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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MachineBasicBlock &MBB = *MI->getParent();
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switch(MI->getDesc().getOpcode()) {
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default:
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return false;
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case Mips::RetRA16:
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ExpandRetRA16(MBB, MI, Mips::JrcRa16);
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break;
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}
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MBB.erase(MI);
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return true;
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}
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/// GetOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
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switch (Opc) {
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default: llvm_unreachable("Illegal opcode!");
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case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
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case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
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case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
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case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
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case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
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case Mips::BtnezX16: return Mips::BteqzX16;
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case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
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case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
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case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
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case Mips::BteqzX16: return Mips::BtnezX16;
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case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
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case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
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case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
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case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
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case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
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case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
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}
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assert(false && "Implement this function.");
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return 0;
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}
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/// Adjust SP by Amount bytes.
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void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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if (isInt<16>(Amount)) {
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if (Amount < 0)
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BuildMI(MBB, I, DL, get(Mips::SaveDecSpF16)). addImm(-Amount);
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else if (Amount > 0)
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BuildMI(MBB, I, DL, get(Mips::RestoreIncSpF16)).addImm(Amount);
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}
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else
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// not implemented for large values yet
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assert(false && "adjust stack pointer amount exceeded");
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}
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unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
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return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
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Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
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Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
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Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
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Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
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Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
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Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
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Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
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Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
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}
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void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Opc) const {
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BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
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}
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const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
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return new Mips16InstrInfo(TM);
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}
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