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c536eed4d8
Test by Nemanja Ivanovic. Since ppc64le implies POWER8 as a minimum, it makes sense that the same features are included. Since the pwr8 processor model will likely be getting new features until the implementation is complete, I created a new list to add these updates to. This will include them in both pwr8 and ppc64le. Furthermore, it seems that it would make sense to compose the feature lists for other processor models (pwr3 and up). Per discussion in the review, I will make this change in a subsequent patch. In order to test the changes, I've added an additional run step to test cases that specify -march=ppc64le -mcpu=pwr8 to omit the -mcpu option. Since the feature lists are the same, the behaviour should be unchanged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227053 91177308-0d34-0410-b5e6-96231b3b80d8
52 lines
1.4 KiB
LLVM
52 lines
1.4 KiB
LLVM
; RUN: llc -march=ppc64le -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -march=ppc64le -mcpu=pwr8 -O0 < %s | FileCheck %s
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; RUN: llc -march=ppc64le < %s | FileCheck %s
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; RUN: llc -march=ppc64le -O0 < %s | FileCheck %s
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; The second run of the test case is to ensure the behaviour is the same
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; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le.
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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@number64 = global i64 10, align 8
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; CHECK: .abiversion 2
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define i64 @use_toc(i64 %a) nounwind {
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entry:
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; CHECK-LABEL: @use_toc
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; CHECK-NEXT: .Ltmp[[TMP1:[0-9]+]]:
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; CHECK-NEXT: addis 2, 12, .TOC.-.Ltmp[[TMP1]]@ha
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; CHECK-NEXT: addi 2, 2, .TOC.-.Ltmp[[TMP1]]@l
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; CHECK-NEXT: .Ltmp[[TMP2:[0-9]+]]:
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; CHECK-NEXT: .localentry use_toc, .Ltmp[[TMP2]]-.Ltmp[[TMP1]]
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; CHECK-NEXT: %entry
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%0 = load i64* @number64, align 8
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%cmp = icmp eq i64 %0, %a
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%conv1 = zext i1 %cmp to i64
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ret i64 %conv1
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}
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declare void @callee()
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define void @use_toc_implicit() nounwind {
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entry:
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; CHECK-LABEL: @use_toc_implicit
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; CHECK-NEXT: .Ltmp[[TMP1:[0-9]+]]:
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; CHECK-NEXT: addis 2, 12, .TOC.-.Ltmp[[TMP1]]@ha
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; CHECK-NEXT: addi 2, 2, .TOC.-.Ltmp[[TMP1]]@l
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; CHECK-NEXT: .Ltmp[[TMP2:[0-9]+]]:
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; CHECK-NEXT: .localentry use_toc_implicit, .Ltmp[[TMP2]]-.Ltmp[[TMP1]]
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; CHECK-NEXT: %entry
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call void @callee()
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ret void
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}
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define i64 @no_toc(i64 %a) nounwind {
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entry:
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; CHECK-LABEL: @no_toc
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; CHECK-NEXT: %entry
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ret i64 %a
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}
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