mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-27 13:30:05 +00:00
8f2a85e099
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210903 91177308-0d34-0410-b5e6-96231b3b80d8
108 lines
3.3 KiB
LLVM
108 lines
3.3 KiB
LLVM
; Test 64-bit compare and swap.
|
|
;
|
|
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
|
|
|
; Check CSG without a displacement.
|
|
define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) {
|
|
; CHECK-LABEL: f1:
|
|
; CHECK: csg %r2, %r3, 0(%r4)
|
|
; CHECK: br %r14
|
|
%pairval = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst seq_cst
|
|
%val = extractvalue { i64, i1 } %pairval, 0
|
|
ret i64 %val
|
|
}
|
|
|
|
; Check the high end of the aligned CSG range.
|
|
define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) {
|
|
; CHECK-LABEL: f2:
|
|
; CHECK: csg %r2, %r3, 524280(%r4)
|
|
; CHECK: br %r14
|
|
%ptr = getelementptr i64 *%src, i64 65535
|
|
%pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
|
|
%val = extractvalue { i64, i1 } %pairval, 0
|
|
ret i64 %val
|
|
}
|
|
|
|
; Check the next doubleword up, which needs separate address logic.
|
|
; Other sequences besides this one would be OK.
|
|
define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) {
|
|
; CHECK-LABEL: f3:
|
|
; CHECK: agfi %r4, 524288
|
|
; CHECK: csg %r2, %r3, 0(%r4)
|
|
; CHECK: br %r14
|
|
%ptr = getelementptr i64 *%src, i64 65536
|
|
%pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
|
|
%val = extractvalue { i64, i1 } %pairval, 0
|
|
ret i64 %val
|
|
}
|
|
|
|
; Check the high end of the negative aligned CSG range.
|
|
define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) {
|
|
; CHECK-LABEL: f4:
|
|
; CHECK: csg %r2, %r3, -8(%r4)
|
|
; CHECK: br %r14
|
|
%ptr = getelementptr i64 *%src, i64 -1
|
|
%pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
|
|
%val = extractvalue { i64, i1 } %pairval, 0
|
|
ret i64 %val
|
|
}
|
|
|
|
; Check the low end of the CSG range.
|
|
define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) {
|
|
; CHECK-LABEL: f5:
|
|
; CHECK: csg %r2, %r3, -524288(%r4)
|
|
; CHECK: br %r14
|
|
%ptr = getelementptr i64 *%src, i64 -65536
|
|
%pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
|
|
%val = extractvalue { i64, i1 } %pairval, 0
|
|
ret i64 %val
|
|
}
|
|
|
|
; Check the next doubleword down, which needs separate address logic.
|
|
; Other sequences besides this one would be OK.
|
|
define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) {
|
|
; CHECK-LABEL: f6:
|
|
; CHECK: agfi %r4, -524296
|
|
; CHECK: csg %r2, %r3, 0(%r4)
|
|
; CHECK: br %r14
|
|
%ptr = getelementptr i64 *%src, i64 -65537
|
|
%pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
|
|
%val = extractvalue { i64, i1 } %pairval, 0
|
|
ret i64 %val
|
|
}
|
|
|
|
; Check that CSG does not allow an index.
|
|
define i64 @f7(i64 %cmp, i64 %swap, i64 %src, i64 %index) {
|
|
; CHECK-LABEL: f7:
|
|
; CHECK: agr %r4, %r5
|
|
; CHECK: csg %r2, %r3, 0(%r4)
|
|
; CHECK: br %r14
|
|
%add1 = add i64 %src, %index
|
|
%ptr = inttoptr i64 %add1 to i64 *
|
|
%pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst seq_cst
|
|
%val = extractvalue { i64, i1 } %pairval, 0
|
|
ret i64 %val
|
|
}
|
|
|
|
; Check that a constant %cmp value is loaded into a register first.
|
|
define i64 @f8(i64 %dummy, i64 %swap, i64 *%ptr) {
|
|
; CHECK-LABEL: f8:
|
|
; CHECK: lghi %r2, 1001
|
|
; CHECK: csg %r2, %r3, 0(%r4)
|
|
; CHECK: br %r14
|
|
%pairval = cmpxchg i64 *%ptr, i64 1001, i64 %swap seq_cst seq_cst
|
|
%val = extractvalue { i64, i1 } %pairval, 0
|
|
ret i64 %val
|
|
}
|
|
|
|
; Check that a constant %swap value is loaded into a register first.
|
|
define i64 @f9(i64 %cmp, i64 *%ptr) {
|
|
; CHECK-LABEL: f9:
|
|
; CHECK: lghi [[SWAP:%r[0-9]+]], 1002
|
|
; CHECK: csg %r2, [[SWAP]], 0(%r3)
|
|
; CHECK: br %r14
|
|
%pairval = cmpxchg i64 *%ptr, i64 %cmp, i64 1002 seq_cst seq_cst
|
|
%val = extractvalue { i64, i1 } %pairval, 0
|
|
ret i64 %val
|
|
}
|