Andrew Trick 92142b3275 The divide unit is not pipeline, but it is still buffered. ... Buffered means a later divide may be executed out-of-order while a prior divide is sitting (buffered) in a reservation station. You can tell it's not pipelined, because operations that use it reserve it for more than one cycle: def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> { let Latency = 25; let ResourceCycles = [1, 10]; } We don't currently distinguish between an unpipeline operation and one that is split into multiple micro-ops requiring the same unit. Except that the later may have NumMicroOps > 1 if they also consume issue/dispatch resources. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178519 91177308-0d34-0410-b5e6-96231b3b80d8		2013-04-02 01:58:47 +00:00
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CodeGen	Merge load/store sequences with adresses: base + index + offset	2013-04-01 18:12:58 +00:00
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IRReader	Fix top-comment header and some indentation	2013-04-01 19:47:56 +00:00
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MC	Mips direct object exception handling regression	2013-04-01 21:55:15 +00:00
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Target	The divide unit is not pipeline, but it is still buffered.	2013-04-02 01:58:47 +00:00
Transforms	Correct assertion condition	2013-04-01 18:13:05 +00:00
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