mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-17 18:31:04 +00:00
5a70dd1d82
Similar to gep (r230786) and load (r230794) changes.
Similar migration script can be used to update test cases, which
successfully migrated all of LLVM and Polly, but about 4 test cases
needed manually changes in Clang.
(this script will read the contents of stdin and massage it into stdout
- wrap it in the 'apply.sh' script shown in previous commits + xargs to
apply it over a large set of test cases)
import fileinput
import sys
import re
rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL)
def conv(match):
line = match.group(1)
line += match.group(4)
line += ", "
line += match.group(2)
return line
line = sys.stdin.read()
off = 0
for match in re.finditer(rep, line):
sys.stdout.write(line[off:match.start()])
sys.stdout.write(conv(match))
off = match.end()
sys.stdout.write(line[off:])
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232184 91177308-0d34-0410-b5e6-96231b3b80d8
192 lines
6.4 KiB
LLVM
192 lines
6.4 KiB
LLVM
; RUN: llc < %s -march=arm64 -mcpu=cyclone -enable-misched=false | FileCheck %s
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target triple = "arm64-apple-ios7.0.0"
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; rdar://13625505
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; Here we have 9 fixed integer arguments the 9th argument in on stack, the
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; varargs start right after at 8-byte alignment.
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define void @fn9(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, ...) nounwind noinline ssp {
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; CHECK-LABEL: fn9:
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; 9th fixed argument
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; CHECK: ldr {{w[0-9]+}}, [sp, #64]
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; CHECK: add [[ARGS:x[0-9]+]], sp, #72
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; CHECK: add {{x[0-9]+}}, [[ARGS]], #8
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; First vararg
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; CHECK: ldr {{w[0-9]+}}, [sp, #72]
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #8
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; Second vararg
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; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #8
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; Third vararg
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; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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%6 = alloca i32, align 4
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%7 = alloca i32, align 4
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%8 = alloca i32, align 4
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%9 = alloca i32, align 4
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%args = alloca i8*, align 8
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%a10 = alloca i32, align 4
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%a11 = alloca i32, align 4
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%a12 = alloca i32, align 4
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store i32 %a1, i32* %1, align 4
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store i32 %a2, i32* %2, align 4
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store i32 %a3, i32* %3, align 4
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store i32 %a4, i32* %4, align 4
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store i32 %a5, i32* %5, align 4
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store i32 %a6, i32* %6, align 4
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store i32 %a7, i32* %7, align 4
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store i32 %a8, i32* %8, align 4
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store i32 %a9, i32* %9, align 4
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%10 = bitcast i8** %args to i8*
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call void @llvm.va_start(i8* %10)
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%11 = va_arg i8** %args, i32
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store i32 %11, i32* %a10, align 4
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%12 = va_arg i8** %args, i32
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store i32 %12, i32* %a11, align 4
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%13 = va_arg i8** %args, i32
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store i32 %13, i32* %a12, align 4
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ret void
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}
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declare void @llvm.va_start(i8*) nounwind
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define i32 @main() nounwind ssp {
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; CHECK-LABEL: main:
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; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
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; CHECK: str {{x[0-9]+}}, [sp, #8]
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; CHECK: str {{w[0-9]+}}, [sp]
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%a1 = alloca i32, align 4
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%a2 = alloca i32, align 4
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%a3 = alloca i32, align 4
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%a4 = alloca i32, align 4
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%a5 = alloca i32, align 4
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%a6 = alloca i32, align 4
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%a7 = alloca i32, align 4
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%a8 = alloca i32, align 4
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%a9 = alloca i32, align 4
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%a10 = alloca i32, align 4
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%a11 = alloca i32, align 4
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%a12 = alloca i32, align 4
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store i32 1, i32* %a1, align 4
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store i32 2, i32* %a2, align 4
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store i32 3, i32* %a3, align 4
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store i32 4, i32* %a4, align 4
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store i32 5, i32* %a5, align 4
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store i32 6, i32* %a6, align 4
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store i32 7, i32* %a7, align 4
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store i32 8, i32* %a8, align 4
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store i32 9, i32* %a9, align 4
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store i32 10, i32* %a10, align 4
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store i32 11, i32* %a11, align 4
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store i32 12, i32* %a12, align 4
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%1 = load i32, i32* %a1, align 4
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%2 = load i32, i32* %a2, align 4
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%3 = load i32, i32* %a3, align 4
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%4 = load i32, i32* %a4, align 4
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%5 = load i32, i32* %a5, align 4
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%6 = load i32, i32* %a6, align 4
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%7 = load i32, i32* %a7, align 4
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%8 = load i32, i32* %a8, align 4
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%9 = load i32, i32* %a9, align 4
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%10 = load i32, i32* %a10, align 4
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%11 = load i32, i32* %a11, align 4
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%12 = load i32, i32* %a12, align 4
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call void (i32, i32, i32, i32, i32, i32, i32, i32, i32, ...)* @fn9(i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12)
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ret i32 0
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}
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;rdar://13668483
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@.str = private unnamed_addr constant [4 x i8] c"fmt\00", align 1
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define void @foo(i8* %fmt, ...) nounwind {
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entry:
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; CHECK-LABEL: foo:
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; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, #0x8
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; CHECK: ldr {{w[0-9]+}}, [sp, #48]
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #15
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; CHECK: and x[[ADDR:[0-9]+]], {{x[0-9]+}}, #0xfffffffffffffff0
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; CHECK: ldr {{q[0-9]+}}, [x[[ADDR]]]
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%fmt.addr = alloca i8*, align 8
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%args = alloca i8*, align 8
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%vc = alloca i32, align 4
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%vv = alloca <4 x i32>, align 16
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store i8* %fmt, i8** %fmt.addr, align 8
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%args1 = bitcast i8** %args to i8*
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call void @llvm.va_start(i8* %args1)
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%0 = va_arg i8** %args, i32
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store i32 %0, i32* %vc, align 4
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%1 = va_arg i8** %args, <4 x i32>
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store <4 x i32> %1, <4 x i32>* %vv, align 16
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ret void
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}
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define void @bar(i32 %x, <4 x i32> %y) nounwind {
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entry:
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; CHECK-LABEL: bar:
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; CHECK: str {{q[0-9]+}}, [sp, #16]
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; CHECK: str {{x[0-9]+}}, [sp]
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%x.addr = alloca i32, align 4
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%y.addr = alloca <4 x i32>, align 16
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store i32 %x, i32* %x.addr, align 4
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store <4 x i32> %y, <4 x i32>* %y.addr, align 16
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%0 = load i32, i32* %x.addr, align 4
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%1 = load <4 x i32>, <4 x i32>* %y.addr, align 16
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call void (i8*, ...)* @foo(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1)
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ret void
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}
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; rdar://13668927
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; When passing 16-byte aligned small structs as vararg, make sure the caller
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; side is 16-byte aligned on stack.
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%struct.s41 = type { i32, i16, i32, i16 }
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define void @foo2(i8* %fmt, ...) nounwind {
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entry:
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; CHECK-LABEL: foo2:
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; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, #0x8
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; CHECK: ldr {{w[0-9]+}}, [sp, #48]
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #15
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; CHECK: and x[[ADDR:[0-9]+]], {{x[0-9]+}}, #0xfffffffffffffff0
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; CHECK: ldr {{q[0-9]+}}, [x[[ADDR]]]
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%fmt.addr = alloca i8*, align 8
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%args = alloca i8*, align 8
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%vc = alloca i32, align 4
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%vs = alloca %struct.s41, align 16
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store i8* %fmt, i8** %fmt.addr, align 8
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%args1 = bitcast i8** %args to i8*
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call void @llvm.va_start(i8* %args1)
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%0 = va_arg i8** %args, i32
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store i32 %0, i32* %vc, align 4
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%ap.cur = load i8*, i8** %args
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%1 = getelementptr i8, i8* %ap.cur, i32 15
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%2 = ptrtoint i8* %1 to i64
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%3 = and i64 %2, -16
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%ap.align = inttoptr i64 %3 to i8*
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%ap.next = getelementptr i8, i8* %ap.align, i32 16
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store i8* %ap.next, i8** %args
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%4 = bitcast i8* %ap.align to %struct.s41*
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%5 = bitcast %struct.s41* %vs to i8*
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%6 = bitcast %struct.s41* %4 to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %5, i8* %6, i64 16, i32 16, i1 false)
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ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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define void @bar2(i32 %x, i128 %s41.coerce) nounwind {
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entry:
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; CHECK-LABEL: bar2:
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; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
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; CHECK: str {{x[0-9]+}}, [sp]
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%x.addr = alloca i32, align 4
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%s41 = alloca %struct.s41, align 16
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store i32 %x, i32* %x.addr, align 4
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%0 = bitcast %struct.s41* %s41 to i128*
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store i128 %s41.coerce, i128* %0, align 1
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%1 = load i32, i32* %x.addr, align 4
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%2 = bitcast %struct.s41* %s41 to i128*
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%3 = load i128, i128* %2, align 1
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call void (i8*, ...)* @foo2(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %1, i128 %3)
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ret void
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}
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