mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-30 21:29:28 +00:00
d04a8d4b33
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
311 lines
11 KiB
C++
311 lines
11 KiB
C++
//===-- RuntimeDyldMachO.cpp - Run-time dynamic linker for MC-JIT -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implementation of the MC-JIT runtime dynamic linker.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "dyld"
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#include "RuntimeDyldMachO.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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using namespace llvm;
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using namespace llvm::object;
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namespace llvm {
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void RuntimeDyldMachO::resolveRelocation(const SectionEntry &Section,
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uint64_t Offset,
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uint64_t Value,
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uint32_t Type,
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int64_t Addend) {
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uint8_t *LocalAddress = Section.Address + Offset;
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uint64_t FinalAddress = Section.LoadAddress + Offset;
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bool isPCRel = (Type >> 24) & 1;
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unsigned MachoType = (Type >> 28) & 0xf;
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unsigned Size = 1 << ((Type >> 25) & 3);
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DEBUG(dbgs() << "resolveRelocation LocalAddress: "
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<< format("%p", LocalAddress)
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<< " FinalAddress: " << format("%p", FinalAddress)
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<< " Value: " << format("%p", Value)
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<< " Addend: " << Addend
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<< " isPCRel: " << isPCRel
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<< " MachoType: " << MachoType
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<< " Size: " << Size
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<< "\n");
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// This just dispatches to the proper target specific routine.
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switch (Arch) {
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default: llvm_unreachable("Unsupported CPU type!");
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case Triple::x86_64:
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resolveX86_64Relocation(LocalAddress,
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FinalAddress,
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(uintptr_t)Value,
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isPCRel,
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MachoType,
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Size,
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Addend);
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break;
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case Triple::x86:
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resolveI386Relocation(LocalAddress,
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FinalAddress,
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(uintptr_t)Value,
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isPCRel,
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MachoType,
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Size,
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Addend);
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break;
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case Triple::arm: // Fall through.
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case Triple::thumb:
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resolveARMRelocation(LocalAddress,
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FinalAddress,
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(uintptr_t)Value,
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isPCRel,
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MachoType,
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Size,
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Addend);
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break;
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}
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}
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bool RuntimeDyldMachO::resolveI386Relocation(uint8_t *LocalAddress,
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uint64_t FinalAddress,
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uint64_t Value,
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bool isPCRel,
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unsigned Type,
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unsigned Size,
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int64_t Addend) {
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if (isPCRel)
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Value -= FinalAddress + 4; // see resolveX86_64Relocation
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switch (Type) {
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default:
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llvm_unreachable("Invalid relocation type!");
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case macho::RIT_Vanilla: {
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uint8_t *p = LocalAddress;
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uint64_t ValueToWrite = Value + Addend;
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for (unsigned i = 0; i < Size; ++i) {
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*p++ = (uint8_t)(ValueToWrite & 0xff);
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ValueToWrite >>= 8;
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}
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}
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case macho::RIT_Difference:
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case macho::RIT_Generic_LocalDifference:
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case macho::RIT_Generic_PreboundLazyPointer:
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return Error("Relocation type not implemented yet!");
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}
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}
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bool RuntimeDyldMachO::resolveX86_64Relocation(uint8_t *LocalAddress,
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uint64_t FinalAddress,
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uint64_t Value,
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bool isPCRel,
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unsigned Type,
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unsigned Size,
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int64_t Addend) {
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// If the relocation is PC-relative, the value to be encoded is the
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// pointer difference.
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if (isPCRel)
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// FIXME: It seems this value needs to be adjusted by 4 for an effective PC
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// address. Is that expected? Only for branches, perhaps?
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Value -= FinalAddress + 4;
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switch(Type) {
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default:
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llvm_unreachable("Invalid relocation type!");
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case macho::RIT_X86_64_Signed1:
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case macho::RIT_X86_64_Signed2:
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case macho::RIT_X86_64_Signed4:
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case macho::RIT_X86_64_Signed:
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case macho::RIT_X86_64_Unsigned:
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case macho::RIT_X86_64_Branch: {
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Value += Addend;
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// Mask in the target value a byte at a time (we don't have an alignment
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// guarantee for the target address, so this is safest).
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uint8_t *p = (uint8_t*)LocalAddress;
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for (unsigned i = 0; i < Size; ++i) {
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*p++ = (uint8_t)Value;
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Value >>= 8;
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}
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return false;
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}
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case macho::RIT_X86_64_GOTLoad:
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case macho::RIT_X86_64_GOT:
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case macho::RIT_X86_64_Subtractor:
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case macho::RIT_X86_64_TLV:
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return Error("Relocation type not implemented yet!");
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}
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}
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bool RuntimeDyldMachO::resolveARMRelocation(uint8_t *LocalAddress,
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uint64_t FinalAddress,
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uint64_t Value,
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bool isPCRel,
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unsigned Type,
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unsigned Size,
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int64_t Addend) {
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// If the relocation is PC-relative, the value to be encoded is the
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// pointer difference.
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if (isPCRel) {
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Value -= FinalAddress;
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// ARM PCRel relocations have an effective-PC offset of two instructions
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// (four bytes in Thumb mode, 8 bytes in ARM mode).
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// FIXME: For now, assume ARM mode.
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Value -= 8;
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}
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switch(Type) {
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default:
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llvm_unreachable("Invalid relocation type!");
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case macho::RIT_Vanilla: {
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// Mask in the target value a byte at a time (we don't have an alignment
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// guarantee for the target address, so this is safest).
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uint8_t *p = (uint8_t*)LocalAddress;
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for (unsigned i = 0; i < Size; ++i) {
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*p++ = (uint8_t)Value;
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Value >>= 8;
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}
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break;
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}
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case macho::RIT_ARM_Branch24Bit: {
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// Mask the value into the target address. We know instructions are
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// 32-bit aligned, so we can do it all at once.
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uint32_t *p = (uint32_t*)LocalAddress;
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// The low two bits of the value are not encoded.
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Value >>= 2;
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// Mask the value to 24 bits.
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Value &= 0xffffff;
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// FIXME: If the destination is a Thumb function (and the instruction
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// is a non-predicated BL instruction), we need to change it to a BLX
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// instruction instead.
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// Insert the value into the instruction.
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*p = (*p & ~0xffffff) | Value;
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break;
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}
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case macho::RIT_ARM_ThumbBranch22Bit:
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case macho::RIT_ARM_ThumbBranch32Bit:
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case macho::RIT_ARM_Half:
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case macho::RIT_ARM_HalfDifference:
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case macho::RIT_Pair:
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case macho::RIT_Difference:
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case macho::RIT_ARM_LocalDifference:
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case macho::RIT_ARM_PreboundLazyPointer:
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return Error("Relocation type not implemented yet!");
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}
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return false;
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}
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void RuntimeDyldMachO::processRelocationRef(const ObjRelocationInfo &Rel,
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ObjectImage &Obj,
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ObjSectionToIDMap &ObjSectionToID,
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const SymbolTableMap &Symbols,
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StubMap &Stubs) {
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uint32_t RelType = (uint32_t) (Rel.Type & 0xffffffffL);
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RelocationValueRef Value;
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SectionEntry &Section = Sections[Rel.SectionID];
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bool isExtern = (RelType >> 27) & 1;
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if (isExtern) {
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// Obtain the symbol name which is referenced in the relocation
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StringRef TargetName;
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const SymbolRef &Symbol = Rel.Symbol;
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Symbol.getName(TargetName);
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// First search for the symbol in the local symbol table
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SymbolTableMap::const_iterator lsi = Symbols.find(TargetName.data());
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if (lsi != Symbols.end()) {
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Value.SectionID = lsi->second.first;
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Value.Addend = lsi->second.second;
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} else {
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// Search for the symbol in the global symbol table
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SymbolTableMap::const_iterator gsi = GlobalSymbolTable.find(TargetName.data());
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if (gsi != GlobalSymbolTable.end()) {
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Value.SectionID = gsi->second.first;
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Value.Addend = gsi->second.second;
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} else
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Value.SymbolName = TargetName.data();
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}
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} else {
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error_code err;
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uint8_t sectionIndex = static_cast<uint8_t>(RelType & 0xFF);
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section_iterator si = Obj.begin_sections(),
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se = Obj.end_sections();
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for (uint8_t i = 1; i < sectionIndex; i++) {
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error_code err;
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si.increment(err);
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if (si == se)
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break;
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}
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assert(si != se && "No section containing relocation!");
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Value.SectionID = findOrEmitSection(Obj, *si, true, ObjSectionToID);
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Value.Addend = 0;
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// FIXME: The size and type of the relocation determines if we can
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// encode an Addend in the target location itself, and if so, how many
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// bytes we should read in order to get it. We don't yet support doing
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// that, and just assuming it's sizeof(intptr_t) is blatantly wrong.
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//Value.Addend = *(const intptr_t *)Target;
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if (Value.Addend) {
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// The MachO addend is an offset from the current section. We need it
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// to be an offset from the destination section
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Value.Addend += Section.ObjAddress - Sections[Value.SectionID].ObjAddress;
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}
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}
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if (Arch == Triple::arm && (RelType & 0xf) == macho::RIT_ARM_Branch24Bit) {
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// This is an ARM branch relocation, need to use a stub function.
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// Look up for existing stub.
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StubMap::const_iterator i = Stubs.find(Value);
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if (i != Stubs.end())
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resolveRelocation(Section, Rel.Offset,
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(uint64_t)Section.Address + i->second,
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RelType, 0);
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else {
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// Create a new stub function.
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Stubs[Value] = Section.StubOffset;
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uint8_t *StubTargetAddr = createStubFunction(Section.Address +
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Section.StubOffset);
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RelocationEntry RE(Rel.SectionID, StubTargetAddr - Section.Address,
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macho::RIT_Vanilla, Value.Addend);
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if (Value.SymbolName)
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addRelocationForSymbol(RE, Value.SymbolName);
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else
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addRelocationForSection(RE, Value.SectionID);
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resolveRelocation(Section, Rel.Offset,
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(uint64_t)Section.Address + Section.StubOffset,
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RelType, 0);
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Section.StubOffset += getMaxStubSize();
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}
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} else {
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RelocationEntry RE(Rel.SectionID, Rel.Offset, RelType, Value.Addend);
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if (Value.SymbolName)
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addRelocationForSymbol(RE, Value.SymbolName);
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else
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addRelocationForSection(RE, Value.SectionID);
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}
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}
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bool RuntimeDyldMachO::isCompatibleFormat(
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const ObjectBuffer *InputBuffer) const {
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if (InputBuffer->getBufferSize() < 4)
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return false;
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StringRef Magic(InputBuffer->getBufferStart(), 4);
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if (Magic == "\xFE\xED\xFA\xCE") return true;
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if (Magic == "\xCE\xFA\xED\xFE") return true;
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if (Magic == "\xFE\xED\xFA\xCF") return true;
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if (Magic == "\xCF\xFA\xED\xFE") return true;
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return false;
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}
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} // end namespace llvm
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