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e93c701cac
The disassembly of VEXT instructions was too lax in the bits checked. This fixes the case where the instruction affects Q-registers but a misaligned lane was specified (should be UNDEFINED). Patch by Amaury de la Vieuville git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8
6 lines
198 B
Plaintext
6 lines
198 B
Plaintext
# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | grep "invalid instruction encoding"
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# invalid imm4 value (0b1xxx)
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# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
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0x8f 0xf9 0xf7 0xf2
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