mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.6 KiB
LLVM
48 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s
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; SI-LABEL: {{^}}vector_umax:
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; SI: v_max_u32_e32
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define void @vector_umax(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 {
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main_body:
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%load = load i32 addrspace(1)* %in, align 4
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%max = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %load)
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%bc = bitcast i32 %max to float
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
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ret void
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}
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; SI-LABEL: {{^}}scalar_umax:
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; SI: s_max_u32
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define void @scalar_umax(i32 %p0, i32 %p1) #0 {
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entry:
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%max = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %p1)
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%bc = bitcast i32 %max to float
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc)
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ret void
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}
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; SI-LABEL: {{^}}trunc_zext_umax:
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; SI: buffer_load_ubyte [[VREG:v[0-9]+]],
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; SI: v_max_u32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]]
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; SI-NOT: and
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; SI: buffer_store_short [[RESULT]],
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define void @trunc_zext_umax(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
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%tmp5 = load i8 addrspace(1)* %src, align 1
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%tmp2 = zext i8 %tmp5 to i32
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%tmp3 = tail call i32 @llvm.AMDGPU.umax(i32 %tmp2, i32 0) nounwind readnone
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%tmp4 = trunc i32 %tmp3 to i8
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%tmp6 = zext i8 %tmp4 to i16
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store i16 %tmp6, i16 addrspace(1)* %out, align 2
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ret void
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}
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; Function Attrs: readnone
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declare i32 @llvm.AMDGPU.umax(i32, i32) #1
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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!0 = metadata !{metadata !"const", null, i32 1}
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