mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
119 lines
3.8 KiB
LLVM
119 lines
3.8 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
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; In this test both the pointer and the offset operands to the
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; BUFFER_LOAD instructions end up being stored in vgprs. This
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; requires us to add the pointer and offset together, store the
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; result in the offset operand (vaddr), and then store 0 in an
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; sgpr register pair and use that for the pointer operand
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; (low 64-bits of srsrc).
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; CHECK-LABEL: {{^}}mubuf:
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; Make sure we aren't using VGPRs for the source operand of s_mov_b64
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; CHECK-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
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; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
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; instructions
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; CHECK: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
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; CHECK: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
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define void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.x() #1
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%1 = call i32 @llvm.r600.read.tidig.y() #1
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%2 = sext i32 %0 to i64
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%3 = sext i32 %1 to i64
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br label %loop
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loop:
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%4 = phi i64 [0, %entry], [%5, %loop]
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%5 = add i64 %2, %4
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%6 = getelementptr i8 addrspace(1)* %in, i64 %5
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%7 = load i8 addrspace(1)* %6, align 1
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%8 = or i64 %5, 1
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%9 = getelementptr i8 addrspace(1)* %in, i64 %8
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%10 = load i8 addrspace(1)* %9, align 1
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%11 = add i8 %7, %10
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%12 = sext i8 %11 to i32
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store i32 %12, i32 addrspace(1)* %out
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%13 = icmp slt i64 %5, 10
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br i1 %13, label %loop, label %done
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done:
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ret void
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}
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declare i32 @llvm.r600.read.tidig.x() #1
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declare i32 @llvm.r600.read.tidig.y() #1
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attributes #1 = { nounwind readnone }
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; Test moving an SMRD instruction to the VALU
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; CHECK-LABEL: {{^}}smrd_valu:
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; CHECK: buffer_load_dword [[OUT:v[0-9]+]]
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; CHECK: buffer_store_dword [[OUT]]
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define void @smrd_valu(i32 addrspace(2)* addrspace(1)* %in, i32 %a, i32 addrspace(1)* %out) {
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entry:
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%0 = icmp ne i32 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = load i32 addrspace(2)* addrspace(1)* %in
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br label %endif
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else:
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%2 = getelementptr i32 addrspace(2)* addrspace(1)* %in
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%3 = load i32 addrspace(2)* addrspace(1)* %2
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br label %endif
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endif:
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%4 = phi i32 addrspace(2)* [%1, %if], [%3, %else]
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%5 = getelementptr i32 addrspace(2)* %4, i32 3000
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%6 = load i32 addrspace(2)* %5
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store i32 %6, i32 addrspace(1)* %out
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ret void
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}
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; Test moving ann SMRD with an immediate offset to the VALU
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; CHECK-LABEL: {{^}}smrd_valu2:
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; CHECK: buffer_load_dword
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define void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%1 = add i32 %0, 4
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%2 = getelementptr [8 x i32] addrspace(2)* %in, i32 %0, i32 4
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%3 = load i32 addrspace(2)* %2
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}s_load_imm_v8i32:
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; CHECK: buffer_load_dwordx4
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; CHECK: buffer_load_dwordx4
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define void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) {
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entry:
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%tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
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%tmp1 = getelementptr inbounds i32 addrspace(2)* %in, i32 %tmp0
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%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)*
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%tmp3 = load <8 x i32> addrspace(2)* %tmp2, align 4
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store <8 x i32> %tmp3, <8 x i32> addrspace(1)* %out, align 32
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ret void
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}
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; CHECK-LABEL: {{^}}s_load_imm_v16i32:
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; CHECK: buffer_load_dwordx4
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; CHECK: buffer_load_dwordx4
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; CHECK: buffer_load_dwordx4
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; CHECK: buffer_load_dwordx4
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define void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) {
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entry:
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%tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
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%tmp1 = getelementptr inbounds i32 addrspace(2)* %in, i32 %tmp0
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%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)*
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%tmp3 = load <16 x i32> addrspace(2)* %tmp2, align 4
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store <16 x i32> %tmp3, <16 x i32> addrspace(1)* %out, align 32
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ret void
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}
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