Kai Nacke 92e28620d3 [mips] Refine octeon instructions seq/seqi/sne/snei
This commit refines the pattern for the octeon seq/seqi/sne/snei instructions.
The target register is set to 0 or 1 according to the result of the comparison.
In C, this is something like

rd = (unsigned long)(rs == rt)

This commit adds a zext to bring the result to i64. With this change the
instruction is selected for this type of code. (gcc produces the same code for
the above C code.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225968 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-14 10:19:09 +00:00
2014-04-07 03:57:04 +00:00
2014-03-02 13:08:46 +00:00
2014-03-12 22:40:22 +00:00
2015-01-07 22:07:33 +00:00

Low Level Virtual Machine (LLVM)
================================

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LLVM backend for 6502
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