llvm-6502/lib/CodeGen
2015-03-10 20:29:59 +00:00
..
AsmPrinter [AsmPrinter][TLOF] Reintroduce AArch64 test 2015-03-10 20:05:23 +00:00
SelectionDAG Teach lowering to correctly handle invoke statepoint and gc results tied to them. Note that we still can not lower gc.relocates for invoke statepoints. 2015-03-10 16:26:48 +00:00
AggressiveAntiDepBreaker.cpp Correct the AggressiveAntiDepBreaker's handling of subregisters defining super registers 2015-01-28 14:44:14 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp Replace std::copy with a back inserter with vector append where feasible 2015-02-28 10:11:12 +00:00
AntiDepBreaker.h
AtomicExpandPass.cpp Mutate TargetLowering::shouldExpandAtomicRMWInIR to specifically dictate how AtomicRMWInsts are expanded. 2015-03-04 15:47:57 +00:00
BasicTargetTransformInfo.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
BranchFolding.cpp Don't evaluate rend() on every iteration of the loop. 2015-03-10 20:29:59 +00:00
BranchFolding.h
CalcSpillWeights.cpp
CallingConvLower.cpp musttail: Only set the inreg flag for fastcall and vectorcall 2015-01-12 23:28:23 +00:00
CMakeLists.txt Remove the Forward Control Flow Integrity pass and its dependencies. 2015-02-27 19:03:38 +00:00
CodeGen.cpp Reland r229944: EH: Prune unreachable resume instructions during Dwarf EH preparation 2015-03-09 22:45:16 +00:00
CodeGenPrepare.cpp DataLayout is mandatory, update the API to reflect it with references. 2015-03-10 02:37:25 +00:00
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp Add the llvm.frameallocate and llvm.recoverframeallocation intrinsics 2015-01-13 00:48:10 +00:00
DFAPacketizer.cpp
DwarfEHPrepare.cpp DataLayout is mandatory, update the API to reflect it with references. 2015-03-10 02:37:25 +00:00
EarlyIfConversion.cpp The subtarget is cached on the MachineFunction. Access it directly. 2015-01-27 07:31:29 +00:00
EdgeBundles.cpp
ErlangGC.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
ExecutionDepsFix.cpp ExecutionDepsFix: Indizes -> Indices. 2015-03-06 18:56:20 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp
GCMetadata.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
GCMetadataPrinter.cpp clang-format all the GC related files (NFC) 2015-01-16 23:16:12 +00:00
GCRootLowering.cpp Get the cached subtarget off the MachineFunction rather than 2015-02-20 18:44:15 +00:00
GCStrategy.cpp Revert GCStrategy ownership changes 2015-01-26 18:26:35 +00:00
GlobalMerge.cpp Rewrite the global merge pass to be subprogram agnostic for now. 2015-02-23 19:28:45 +00:00
IfConversion.cpp Simplify expressions involving boolean constants with clang-tidy 2015-03-09 01:57:13 +00:00
InlineSpiller.cpp Prefer SmallVector::append/insert over push_back loops. 2015-02-17 15:29:18 +00:00
InterferenceCache.cpp Make static variables const if possible. Makes them go into a read-only section. 2015-03-08 16:07:39 +00:00
InterferenceCache.h Make static variables const if possible. Makes them go into a read-only section. 2015-03-08 16:07:39 +00:00
IntrinsicLowering.cpp
LatencyPriorityQueue.cpp Remove LatencyPriorityQueue::dump because it relies on an implicit copy ctor which is deprecated in C++11 (due to the presence of a user-declare dtor in the base class) 2015-03-03 21:16:56 +00:00
LexicalScopes.cpp AsmPrinter: Stop creating DebugLocs 2015-02-17 00:02:27 +00:00
LiveDebugVariables.cpp Rewrite MachineOperand::print and MachineInstr::print to avoid 2015-02-27 00:11:34 +00:00
LiveDebugVariables.h [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
LiveInterval.cpp Recommit r231168: unique_ptrify LiveRange::segmentSet 2015-03-04 01:20:33 +00:00
LiveIntervalAnalysis.cpp [LiveIntervalAnalysis] Speed up creation of live ranges for physical registers 2015-02-06 18:42:41 +00:00
LiveIntervalUnion.cpp LiveIntervalUnion: Allow specification of liverange when unifying/extracting. 2014-12-10 01:12:59 +00:00
LivePhysRegs.cpp
LiveRangeCalc.cpp LiveRangeCalc: Don't start liveranges of PHI instruction at the block begin. 2015-02-20 23:43:14 +00:00
LiveRangeCalc.h LiveRangeCalc: Rename some parameters from kill to use, NFC. 2015-02-18 01:50:52 +00:00
LiveRangeEdit.cpp MachineRegisterInfo can access TII off of the MachineFunction's 2015-01-27 01:15:16 +00:00
LiveRegMatrix.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
LiveStackAnalysis.cpp Recommit r231168: unique_ptrify LiveRange::segmentSet 2015-03-04 01:20:33 +00:00
LiveVariables.cpp
LLVMBuild.txt
LLVMTargetMachine.cpp Remove the Forward Control Flow Integrity pass and its dependencies. 2015-02-27 19:03:38 +00:00
LocalStackSlotAllocation.cpp
MachineBasicBlock.cpp Rewrite MachineOperand::print and MachineInstr::print to avoid 2015-02-27 00:11:34 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp [MBP] Use range based for-loops throughout this code. Several had 2015-03-05 03:19:05 +00:00
MachineBranchProbabilityInfo.cpp
MachineCombiner.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
MachineCopyPropagation.cpp
MachineCSE.cpp MachineCSE: Clear dead-def flag on CSE. 2015-02-04 19:35:16 +00:00
MachineDominanceFrontier.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
MachineDominators.cpp MachineDominators: Move applySplitCriticalEdges into the cpp file. 2015-02-27 23:13:13 +00:00
MachineFunction.cpp DataLayout is mandatory, update the API to reflect it with references. 2015-03-10 02:37:25 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
MachineFunctionPrinterPass.cpp Rename argument strings of codegen passes to avoid collisions with command line 2014-12-13 04:52:04 +00:00
MachineInstr.cpp Rewrite MachineOperand::print and MachineInstr::print to avoid 2015-02-27 00:11:34 +00:00
MachineInstrBundle.cpp
MachineLICM.cpp Small cleanup of MachineLICM.cpp 2015-02-05 22:39:46 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp Unify the two EH personality classification routines I wrote 2015-02-14 00:21:02 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegionInfo.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
MachineRegisterInfo.cpp MachineRegisterInfo can access TII off of the MachineFunction's 2015-01-27 01:15:16 +00:00
MachineScheduler.cpp The subtarget is cached on the MachineFunction. Access it directly. 2015-01-27 07:31:29 +00:00
MachineSink.cpp
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp The subtarget is cached on the MachineFunction. Access it directly. 2015-01-27 07:31:29 +00:00
MachineVerifier.cpp Rewrite MachineOperand::print and MachineInstr::print to avoid 2015-02-27 00:11:34 +00:00
Makefile
module.modulemap
OcamlGC.cpp Revert GCStrategy ownership changes 2015-01-26 18:26:35 +00:00
OptimizePHIs.cpp
Passes.cpp [PM] Remove the old 'PassManager.h' header file at the top level of 2015-02-13 10:01:29 +00:00
PeepholeOptimizer.cpp Simplify expressions involving boolean constants with clang-tidy 2015-03-09 01:57:13 +00:00
PHIElimination.cpp During PHI elimination, split critical edges that move copies out of loops. 2015-03-03 10:23:11 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp The subtarget is cached on the MachineFunction. Access it directly. 2015-01-27 07:31:29 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp Replace llvm.frameallocate with llvm.frameescape 2015-03-05 18:26:34 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp [RegAllocGreedy] Introduce a late pass to repair broken hints. 2015-01-08 01:16:39 +00:00
RegAllocBase.h [RegAllocGreedy] Introduce a late pass to repair broken hints. 2015-01-08 01:16:39 +00:00
RegAllocBasic.cpp
RegAllocFast.cpp
RegAllocGreedy.cpp [RegAllocGreedy] Introduce a late pass to repair broken hints. 2015-01-08 01:16:39 +00:00
RegAllocPBQP.cpp [PBQP] Use a local bit-matrix to speedup searching an edge in the graph. 2015-03-05 09:12:59 +00:00
RegisterClassInfo.cpp Silence more static analyzer warnings. 2014-12-15 18:48:43 +00:00
RegisterCoalescer.cpp RegisterCoalescer: Gracefully continue if subrange merging fails. 2015-03-04 00:43:50 +00:00
RegisterCoalescer.h
RegisterPressure.cpp
RegisterScavenging.cpp
ScheduleDAG.cpp Replace some uses of getSubtargetImpl with the cached version 2015-01-27 08:48:42 +00:00
ScheduleDAGInstrs.cpp DataLayout is mandatory, update the API to reflect it with references. 2015-03-10 02:37:25 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
ShadowStackGCLowering.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
SjLjEHPrepare.cpp Replace some uses of getSubtargetImpl with the cached version 2015-01-27 08:48:42 +00:00
SlotIndexes.cpp
Spiller.h
SpillPlacement.cpp
SpillPlacement.h
SplitKit.cpp LiveIntervalAnalysis: Factor out code to update liveness on vreg def removal 2015-01-21 19:02:30 +00:00
SplitKit.h
StackColoring.cpp StackColoring: Move set instead of copying. NFC. 2015-02-28 20:14:38 +00:00
StackMapLivenessAnalysis.cpp [StackMaps] Allow the target to pre-process the live-out mask 2015-01-13 17:47:59 +00:00
StackMaps.cpp Move DataLayout back to the TargetMachine from TargetSubtargetInfo 2015-01-26 19:03:15 +00:00
StackProtector.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
StackSlotColoring.cpp Recommit r231175: Change LiveStackAnalysis::SS2IntervalMap from std::map to std::unordered_map 2015-03-04 01:15:53 +00:00
StatepointExampleGC.cpp Revert GCStrategy ownership changes 2015-01-26 18:26:35 +00:00
TailDuplication.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
TargetFrameLoweringImpl.cpp [X86] Convert esp-relative movs of function arguments to pushes, step 2 2015-02-01 16:56:04 +00:00
TargetInstrInfo.cpp ArrayRefize memory operand folding. NFC. 2015-02-28 12:04:00 +00:00
TargetLoweringBase.cpp DataLayout is mandatory, update the API to reflect it with references. 2015-03-10 02:37:25 +00:00
TargetLoweringObjectFileImpl.cpp [AsmPrinter][TLOF] 32-bit MachO support for replacing GOT equivalents 2015-03-06 13:49:05 +00:00
TargetOptionsImpl.cpp Migrate ABIName to MCTargetOptions so that it can be shared between 2015-01-14 00:50:31 +00:00
TargetRegisterInfo.cpp
TargetSchedule.cpp
TwoAddressInstructionPass.cpp Revert the test commit. 2015-03-04 17:44:22 +00:00
UnreachableBlockElim.cpp Replace size method call of containers to empty method where appropriate 2015-01-15 11:41:30 +00:00
VirtRegMap.cpp LiveInterval: Use range based for loops for subregister ranges. 2014-12-11 00:59:06 +00:00
WinEHPrepare.cpp DataLayout is mandatory, update the API to reflect it with references. 2015-03-10 02:37:25 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.