mirror of
https://github.com/c64scene-ar/llvm-6502.git
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78ce816d3f
If some commits are happy, and some commits are sad, this is a sad commit. It
is sad because it restricts instruction scheduling to work around a binutils
linker bug, and moreover, one that may never be fixed. On 2012-05-21, GCC was
updated not to produce code triggering this bug, and now we'll do the same...
When resolving an address using the ELF ABI TOC pointer, two relocations are
generally required: one for the high part and one for the low part. Only
the high part generally explicitly depends on r2 (the TOC pointer). And, so,
we might produce code like this:
.Ltmp526:
addis 3, 2, .LC12@toc@ha
.Ltmp1628:
std 2, 40(1)
ld 5, 0(27)
ld 2, 8(27)
ld 11, 16(27)
ld 3, .LC12@toc@l(3)
rldicl 4, 4, 0, 32
mtctr 5
bctrl
ld 2, 40(1)
And there is nothing wrong with this code, as such, but there is a linker bug
in binutils (https://sourceware.org/bugzilla/show_bug.cgi?id=18414) that will
misoptimize this code sequence to this:
nop
std r2,40(r1)
ld r5,0(r27)
ld r2,8(r27)
ld r11,16(r27)
ld r3,-32472(r2)
clrldi r4,r4,32
mtctr r5
bctrl
ld r2,40(r1)
because the linker does not know (and does not check) that the value in r2
changed in between the instruction using the .LC12@toc@ha (TOC-relative)
relocation and the instruction using the .LC12@toc@l(3) relocation.
Because it finds these instructions using the relocations (and not by
scanning the instructions), it has been asserted that there is no good way
to detect the change of r2 in between. As a result, this bug may never be
fixed (i.e. it may become part of the definition of the ABI). GCC was
updated to add extra dependencies on r2 to instructions using the @toc@l
relocations to avoid this problem, and we'll do the same here.
This is done as a separate pass because:
1. These extra r2 dependencies are not really properties of the
instructions, but rather due to a linker bug, and maybe one day we'll be
able to get rid of them when targeting linkers without this bug (and,
thus, keeping the logic centralized here will make that
straightforward).
2. There are ISel-level peephole optimizations that propagate the @toc@l
relocations to some user instructions, and so the exta dependencies do
not apply only to a fixed set of instructions (without undesirable
definition replication).
The test case was reduced with the help of bugpoint, with minimal cleaning. I'm
looking forward to our upcoming MI serialization support, and with that, much
better tests can be created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237556 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.3 KiB
CMake
48 lines
1.3 KiB
CMake
set(LLVM_TARGET_DEFINITIONS PPC.td)
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tablegen(LLVM PPCGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM PPCGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM PPCGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM PPCGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM PPCGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel)
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tablegen(LLVM PPCGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM PPCGenSubtargetInfo.inc -gen-subtarget)
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add_public_tablegen_target(PowerPCCommonTableGen)
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add_llvm_target(PowerPCCodeGen
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PPCAsmPrinter.cpp
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PPCBranchSelector.cpp
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PPCCTRLoops.cpp
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PPCHazardRecognizers.cpp
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PPCInstrInfo.cpp
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PPCISelDAGToDAG.cpp
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PPCISelLowering.cpp
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PPCEarlyReturn.cpp
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PPCFastISel.cpp
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PPCFrameLowering.cpp
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PPCLoopDataPrefetch.cpp
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PPCLoopPreIncPrep.cpp
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PPCMCInstLower.cpp
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PPCMachineFunctionInfo.cpp
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PPCRegisterInfo.cpp
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PPCSubtarget.cpp
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PPCTargetMachine.cpp
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PPCTargetObjectFile.cpp
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PPCTargetTransformInfo.cpp
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PPCTOCRegDeps.cpp
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PPCSelectionDAGInfo.cpp
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PPCTLSDynamicCall.cpp
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PPCVSXCopy.cpp
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PPCVSXFMAMutate.cpp
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PPCVSXSwapRemoval.cpp
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)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(InstPrinter)
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add_subdirectory(TargetInfo)
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add_subdirectory(MCTargetDesc)
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