mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-25 14:32:53 +00:00
c35497fc2a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31294 91177308-0d34-0410-b5e6-96231b3b80d8
914 lines
31 KiB
C++
914 lines
31 KiB
C++
//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the ARM target.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMTargetMachine.h"
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#include "llvm/CallingConv.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Constants.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/Debug.h"
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#include <iostream>
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#include <vector>
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using namespace llvm;
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namespace {
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class ARMTargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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public:
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ARMTargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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};
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}
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ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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addRegisterClass(MVT::i32, ARM::IntRegsRegisterClass);
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addRegisterClass(MVT::f32, ARM::FPRegsRegisterClass);
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addRegisterClass(MVT::f64, ARM::DFPRegsRegisterClass);
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setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Expand);
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setOperationAction(ISD::SETCC, MVT::f64, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BRIND, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f32, Custom);
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setOperationAction(ISD::BR_CC, MVT::f64, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SDIV, MVT::i32, Expand);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::VACOPY, MVT::Other, Expand);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
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setStackPointerRegisterToSaveRestore(ARM::R13);
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setSchedulingPreference(SchedulingForRegPressure);
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computeRegisterProperties();
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}
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namespace llvm {
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namespace ARMISD {
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
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/// CALL - A direct function call.
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CALL,
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/// Return with a flag operand.
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RET_FLAG,
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CMP,
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SELECT,
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BR,
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FSITOS,
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FTOSIS,
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FSITOD,
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FTOSID,
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FUITOS,
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FTOUIS,
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FUITOD,
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FTOUID,
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FMRRD,
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FMDRR,
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FMSTAT
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};
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}
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}
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/// DAGFPCCToARMCC - Convert a DAG fp condition code to an ARM CC
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// Unordered = !N & !Z & C & V = V
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// Ordered = N | Z | !C | !V = N | Z | !V
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static ARMCC::CondCodes DAGFPCCToARMCC(ISD::CondCode CC) {
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switch (CC) {
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default:
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assert(0 && "Unknown fp condition code!");
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// SETOEQ = (N | Z | !V) & Z = Z = EQ
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case ISD::SETEQ:
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case ISD::SETOEQ: return ARMCC::EQ;
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// SETOGT = (N | Z | !V) & !N & !Z = !V &!N &!Z = (N = V) & !Z = GT
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case ISD::SETGT:
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case ISD::SETOGT: return ARMCC::GT;
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// SETOGE = (N | Z | !V) & !N = (Z | !V) & !N = !V & !N = GE
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case ISD::SETGE:
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case ISD::SETOGE: return ARMCC::GE;
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// SETOLT = (N | Z | !V) & N = N = MI
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case ISD::SETLT:
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case ISD::SETOLT: return ARMCC::MI;
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// SETOLE = (N | Z | !V) & (N | Z) = N | Z = !C | Z = LS
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case ISD::SETLE:
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case ISD::SETOLE: return ARMCC::LS;
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// SETONE = (N | Z | !V) & !Z = (N | !V) & Z = !V & Z = Z = NE
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case ISD::SETNE:
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case ISD::SETONE: return ARMCC::NE;
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// SETO = N | Z | !V = Z | !V = !V = VC
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case ISD::SETO: return ARMCC::VC;
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// SETUO = V = VS
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case ISD::SETUO: return ARMCC::VS;
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// SETUEQ = V | Z = ??
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// SETUGT = V | (!Z & !N) = !Z & !N = !Z & C = HI
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case ISD::SETUGT: return ARMCC::HI;
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// SETUGE = V | !N = !N = PL
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case ISD::SETUGE: return ARMCC::PL;
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// SETULT = V | N = ??
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// SETULE = V | Z | N = ??
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// SETUNE = V | !Z = !Z = NE
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case ISD::SETUNE: return ARMCC::NE;
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}
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}
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/// DAGIntCCToARMCC - Convert a DAG integer condition code to an ARM CC
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static ARMCC::CondCodes DAGIntCCToARMCC(ISD::CondCode CC) {
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switch (CC) {
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default:
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assert(0 && "Unknown integer condition code!");
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case ISD::SETEQ: return ARMCC::EQ;
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case ISD::SETNE: return ARMCC::NE;
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case ISD::SETLT: return ARMCC::LT;
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case ISD::SETLE: return ARMCC::LE;
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case ISD::SETGT: return ARMCC::GT;
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case ISD::SETGE: return ARMCC::GE;
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case ISD::SETULT: return ARMCC::CC;
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case ISD::SETULE: return ARMCC::LS;
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case ISD::SETUGT: return ARMCC::HI;
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case ISD::SETUGE: return ARMCC::CS;
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}
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}
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const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case ARMISD::CALL: return "ARMISD::CALL";
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case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
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case ARMISD::SELECT: return "ARMISD::SELECT";
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case ARMISD::CMP: return "ARMISD::CMP";
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case ARMISD::BR: return "ARMISD::BR";
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case ARMISD::FSITOS: return "ARMISD::FSITOS";
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case ARMISD::FTOSIS: return "ARMISD::FTOSIS";
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case ARMISD::FSITOD: return "ARMISD::FSITOD";
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case ARMISD::FTOSID: return "ARMISD::FTOSID";
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case ARMISD::FUITOS: return "ARMISD::FUITOS";
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case ARMISD::FTOUIS: return "ARMISD::FTOUIS";
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case ARMISD::FUITOD: return "ARMISD::FUITOD";
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case ARMISD::FTOUID: return "ARMISD::FTOUID";
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case ARMISD::FMRRD: return "ARMISD::FMRRD";
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case ARMISD::FMDRR: return "ARMISD::FMDRR";
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case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
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}
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}
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class ArgumentLayout {
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std::vector<bool> is_reg;
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std::vector<unsigned> pos;
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std::vector<MVT::ValueType> types;
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public:
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ArgumentLayout(const std::vector<MVT::ValueType> &Types) {
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types = Types;
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unsigned RegNum = 0;
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unsigned StackOffset = 0;
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for(std::vector<MVT::ValueType>::const_iterator I = Types.begin();
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I != Types.end();
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++I) {
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MVT::ValueType VT = *I;
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assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
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unsigned size = MVT::getSizeInBits(VT)/32;
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RegNum = ((RegNum + size - 1) / size) * size;
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if (RegNum < 4) {
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pos.push_back(RegNum);
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is_reg.push_back(true);
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RegNum += size;
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} else {
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unsigned bytes = size * 32/8;
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StackOffset = ((StackOffset + bytes - 1) / bytes) * bytes;
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pos.push_back(StackOffset);
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is_reg.push_back(false);
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StackOffset += bytes;
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}
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}
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}
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unsigned getRegisterNum(unsigned argNum) {
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assert(isRegister(argNum));
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return pos[argNum];
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}
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unsigned getOffset(unsigned argNum) {
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assert(isOffset(argNum));
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return pos[argNum];
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}
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unsigned isRegister(unsigned argNum) {
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assert(argNum < is_reg.size());
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return is_reg[argNum];
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}
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unsigned isOffset(unsigned argNum) {
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return !isRegister(argNum);
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}
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MVT::ValueType getType(unsigned argNum) {
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assert(argNum < types.size());
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return types[argNum];
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}
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unsigned getStackSize(void) {
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int last = is_reg.size() - 1;
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if (last < 0)
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return 0;
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if (isRegister(last))
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return 0;
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return getOffset(last) + MVT::getSizeInBits(getType(last))/8;
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}
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int lastRegArg(void) {
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int size = is_reg.size();
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int last = 0;
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while(last < size && isRegister(last))
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last++;
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last--;
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return last;
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}
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int lastRegNum(void) {
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int l = lastRegArg();
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if (l < 0)
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return -1;
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unsigned r = getRegisterNum(l);
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MVT::ValueType t = getType(l);
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assert(t == MVT::i32 || t == MVT::f32 || t == MVT::f64);
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if (t == MVT::f64)
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return r + 1;
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return r;
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}
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};
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// This transforms a ISD::CALL node into a
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// callseq_star <- ARMISD:CALL <- callseq_end
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// chain
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static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Chain = Op.getOperand(0);
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unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
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assert((CallConv == CallingConv::C ||
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CallConv == CallingConv::Fast)
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&& "unknown calling convention");
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
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SDOperand Callee = Op.getOperand(4);
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unsigned NumOps = (Op.getNumOperands() - 5) / 2;
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SDOperand StackPtr = DAG.getRegister(ARM::R13, MVT::i32);
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static const unsigned regs[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3
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};
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std::vector<MVT::ValueType> Types;
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for (unsigned i = 0; i < NumOps; ++i) {
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MVT::ValueType VT = Op.getOperand(5+2*i).getValueType();
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Types.push_back(VT);
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}
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ArgumentLayout Layout(Types);
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unsigned NumBytes = Layout.getStackSize();
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Chain = DAG.getCALLSEQ_START(Chain,
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DAG.getConstant(NumBytes, MVT::i32));
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//Build a sequence of stores
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std::vector<SDOperand> MemOpChains;
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for (unsigned i = Layout.lastRegArg() + 1; i < NumOps; ++i) {
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SDOperand Arg = Op.getOperand(5+2*i);
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unsigned ArgOffset = Layout.getOffset(i);
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SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
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PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
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}
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// If the callee is a GlobalAddress node (quite common, every direct call is)
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// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
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// Likewise ExternalSymbol -> TargetExternalSymbol.
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assert(Callee.getValueType() == MVT::i32);
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
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else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
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// If this is a direct call, pass the chain and the callee.
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assert (Callee.Val);
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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// Build a sequence of copy-to-reg nodes chained together with token chain
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// and flag operands which copy the outgoing args into the appropriate regs.
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SDOperand InFlag;
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for (int i = 0, e = Layout.lastRegArg(); i <= e; ++i) {
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SDOperand Arg = Op.getOperand(5+2*i);
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unsigned RegNum = Layout.getRegisterNum(i);
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unsigned Reg1 = regs[RegNum];
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MVT::ValueType VT = Layout.getType(i);
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assert(VT == Arg.getValueType());
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assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
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// Add argument register to the end of the list so that it is known live
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// into the call.
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Ops.push_back(DAG.getRegister(Reg1, MVT::i32));
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if (VT == MVT::f64) {
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unsigned Reg2 = regs[RegNum + 1];
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SDOperand SDReg1 = DAG.getRegister(Reg1, MVT::i32);
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SDOperand SDReg2 = DAG.getRegister(Reg2, MVT::i32);
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Ops.push_back(DAG.getRegister(Reg2, MVT::i32));
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SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag);
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SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg, InFlag};
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Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, InFlag.Val ? 5 : 4);
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} else {
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if (VT == MVT::f32)
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Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg);
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Chain = DAG.getCopyToReg(Chain, Reg1, Arg, InFlag);
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}
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InFlag = Chain.getValue(1);
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}
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std::vector<MVT::ValueType> NodeTys;
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NodeTys.push_back(MVT::Other); // Returns a chain
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NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
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unsigned CallOpc = ARMISD::CALL;
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if (InFlag.Val)
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Ops.push_back(InFlag);
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Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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std::vector<SDOperand> ResultVals;
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NodeTys.clear();
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// If the call has results, copy the values out of the ret val registers.
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MVT::ValueType VT = Op.Val->getValueType(0);
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if (VT != MVT::Other) {
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assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
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SDOperand Value1 = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
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Chain = Value1.getValue(1);
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InFlag = Value1.getValue(2);
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NodeTys.push_back(VT);
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if (VT == MVT::i32) {
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ResultVals.push_back(Value1);
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if (Op.Val->getValueType(1) == MVT::i32) {
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SDOperand Value2 = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, InFlag);
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Chain = Value2.getValue(1);
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ResultVals.push_back(Value2);
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NodeTys.push_back(VT);
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}
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}
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if (VT == MVT::f32) {
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SDOperand Value = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Value1);
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ResultVals.push_back(Value);
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}
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if (VT == MVT::f64) {
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SDOperand Value2 = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, InFlag);
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Chain = Value2.getValue(1);
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SDOperand Value = DAG.getNode(ARMISD::FMDRR, MVT::f64, Value1, Value2);
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ResultVals.push_back(Value);
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}
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}
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|
|
Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
|
|
DAG.getConstant(NumBytes, MVT::i32));
|
|
NodeTys.push_back(MVT::Other);
|
|
|
|
if (ResultVals.empty())
|
|
return Chain;
|
|
|
|
ResultVals.push_back(Chain);
|
|
SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
|
|
ResultVals.size());
|
|
return Res.getValue(Op.ResNo);
|
|
}
|
|
|
|
static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
|
|
SDOperand Copy;
|
|
SDOperand Chain = Op.getOperand(0);
|
|
SDOperand R0 = DAG.getRegister(ARM::R0, MVT::i32);
|
|
SDOperand R1 = DAG.getRegister(ARM::R1, MVT::i32);
|
|
|
|
switch(Op.getNumOperands()) {
|
|
default:
|
|
assert(0 && "Do not know how to return this many arguments!");
|
|
abort();
|
|
case 1: {
|
|
SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
|
|
return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
|
|
}
|
|
case 3: {
|
|
SDOperand Val = Op.getOperand(1);
|
|
assert(Val.getValueType() == MVT::i32 ||
|
|
Val.getValueType() == MVT::f32 ||
|
|
Val.getValueType() == MVT::f64);
|
|
|
|
if (Val.getValueType() == MVT::f64) {
|
|
SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag);
|
|
SDOperand Ops[] = {Chain, R0, R1, Val};
|
|
Copy = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4);
|
|
} else {
|
|
if (Val.getValueType() == MVT::f32)
|
|
Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
|
|
Copy = DAG.getCopyToReg(Chain, R0, Val, SDOperand());
|
|
}
|
|
|
|
if (DAG.getMachineFunction().liveout_empty()) {
|
|
DAG.getMachineFunction().addLiveOut(ARM::R0);
|
|
if (Val.getValueType() == MVT::f64)
|
|
DAG.getMachineFunction().addLiveOut(ARM::R1);
|
|
}
|
|
break;
|
|
}
|
|
case 5:
|
|
Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
|
|
Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
|
|
// If we haven't noted the R0+R1 are live out, do so now.
|
|
if (DAG.getMachineFunction().liveout_empty()) {
|
|
DAG.getMachineFunction().addLiveOut(ARM::R0);
|
|
DAG.getMachineFunction().addLiveOut(ARM::R1);
|
|
}
|
|
break;
|
|
}
|
|
|
|
//We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
|
|
return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
|
|
}
|
|
|
|
static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
|
|
MVT::ValueType PtrVT = Op.getValueType();
|
|
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
|
|
Constant *C = CP->getConstVal();
|
|
SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
|
|
|
|
return CPI;
|
|
}
|
|
|
|
static SDOperand LowerGlobalAddress(SDOperand Op,
|
|
SelectionDAG &DAG) {
|
|
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
|
int alignment = 2;
|
|
SDOperand CPAddr = DAG.getConstantPool(GV, MVT::i32, alignment);
|
|
return DAG.getLoad(MVT::i32, DAG.getEntryNode(), CPAddr, NULL, 0);
|
|
}
|
|
|
|
static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
|
|
unsigned VarArgsFrameIndex) {
|
|
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
|
// memory location argument.
|
|
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
|
|
SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
|
|
SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
|
|
return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
|
|
SV->getOffset());
|
|
}
|
|
|
|
static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
|
|
int &VarArgsFrameIndex) {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
SSARegMap *RegMap = MF.getSSARegMap();
|
|
unsigned NumArgs = Op.Val->getNumValues()-1;
|
|
SDOperand Root = Op.getOperand(0);
|
|
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
|
|
static const unsigned REGS[] = {
|
|
ARM::R0, ARM::R1, ARM::R2, ARM::R3
|
|
};
|
|
|
|
std::vector<MVT::ValueType> Types(Op.Val->value_begin(), Op.Val->value_end() - 1);
|
|
ArgumentLayout Layout(Types);
|
|
|
|
std::vector<SDOperand> ArgValues;
|
|
for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) {
|
|
MVT::ValueType VT = Types[ArgNo];
|
|
|
|
SDOperand Value;
|
|
if (Layout.isRegister(ArgNo)) {
|
|
assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
|
|
unsigned RegNum = Layout.getRegisterNum(ArgNo);
|
|
unsigned Reg1 = REGS[RegNum];
|
|
unsigned VReg1 = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
|
|
SDOperand Value1 = DAG.getCopyFromReg(Root, VReg1, MVT::i32);
|
|
MF.addLiveIn(Reg1, VReg1);
|
|
if (VT == MVT::f64) {
|
|
unsigned Reg2 = REGS[RegNum + 1];
|
|
unsigned VReg2 = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
|
|
SDOperand Value2 = DAG.getCopyFromReg(Root, VReg2, MVT::i32);
|
|
MF.addLiveIn(Reg2, VReg2);
|
|
Value = DAG.getNode(ARMISD::FMDRR, MVT::f64, Value1, Value2);
|
|
} else {
|
|
Value = Value1;
|
|
if (VT == MVT::f32)
|
|
Value = DAG.getNode(ISD::BIT_CONVERT, VT, Value);
|
|
}
|
|
} else {
|
|
// If the argument is actually used, emit a load from the right stack
|
|
// slot.
|
|
if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
|
|
unsigned Offset = Layout.getOffset(ArgNo);
|
|
unsigned Size = MVT::getSizeInBits(VT)/8;
|
|
int FI = MFI->CreateFixedObject(Size, Offset);
|
|
SDOperand FIN = DAG.getFrameIndex(FI, VT);
|
|
Value = DAG.getLoad(VT, Root, FIN, NULL, 0);
|
|
} else {
|
|
Value = DAG.getNode(ISD::UNDEF, VT);
|
|
}
|
|
}
|
|
ArgValues.push_back(Value);
|
|
}
|
|
|
|
unsigned NextRegNum = Layout.lastRegNum() + 1;
|
|
|
|
if (isVarArg) {
|
|
//If this function is vararg we must store the remaing
|
|
//registers so that they can be acessed with va_start
|
|
VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8,
|
|
-16 + NextRegNum * 4);
|
|
|
|
SmallVector<SDOperand, 4> MemOps;
|
|
for (unsigned RegNo = NextRegNum; RegNo < 4; ++RegNo) {
|
|
int RegOffset = - (4 - RegNo) * 4;
|
|
int FI = MFI->CreateFixedObject(MVT::getSizeInBits(MVT::i32)/8,
|
|
RegOffset);
|
|
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
|
|
|
|
unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
|
|
MF.addLiveIn(REGS[RegNo], VReg);
|
|
|
|
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
|
|
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
|
|
MemOps.push_back(Store);
|
|
}
|
|
Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
|
|
}
|
|
|
|
ArgValues.push_back(Root);
|
|
|
|
// Return the new list of results.
|
|
std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
|
|
Op.Val->value_end());
|
|
return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
|
|
}
|
|
|
|
static SDOperand GetCMP(ISD::CondCode CC, SDOperand LHS, SDOperand RHS,
|
|
SelectionDAG &DAG) {
|
|
MVT::ValueType vt = LHS.getValueType();
|
|
assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64);
|
|
|
|
SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
|
|
|
|
if (vt != MVT::i32)
|
|
Cmp = DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
|
|
return Cmp;
|
|
}
|
|
|
|
static SDOperand GetARMCC(ISD::CondCode CC, MVT::ValueType vt,
|
|
SelectionDAG &DAG) {
|
|
assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64);
|
|
if (vt == MVT::i32)
|
|
return DAG.getConstant(DAGIntCCToARMCC(CC), MVT::i32);
|
|
else
|
|
return DAG.getConstant(DAGFPCCToARMCC(CC), MVT::i32);
|
|
}
|
|
|
|
static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
|
|
SDOperand LHS = Op.getOperand(0);
|
|
SDOperand RHS = Op.getOperand(1);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
|
|
SDOperand TrueVal = Op.getOperand(2);
|
|
SDOperand FalseVal = Op.getOperand(3);
|
|
SDOperand Cmp = GetCMP(CC, LHS, RHS, DAG);
|
|
SDOperand ARMCC = GetARMCC(CC, LHS.getValueType(), DAG);
|
|
return DAG.getNode(ARMISD::SELECT, MVT::i32, TrueVal, FalseVal, ARMCC, Cmp);
|
|
}
|
|
|
|
static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) {
|
|
SDOperand Chain = Op.getOperand(0);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
|
|
SDOperand LHS = Op.getOperand(2);
|
|
SDOperand RHS = Op.getOperand(3);
|
|
SDOperand Dest = Op.getOperand(4);
|
|
SDOperand Cmp = GetCMP(CC, LHS, RHS, DAG);
|
|
SDOperand ARMCC = GetARMCC(CC, LHS.getValueType(), DAG);
|
|
return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp);
|
|
}
|
|
|
|
static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
|
|
SDOperand IntVal = Op.getOperand(0);
|
|
assert(IntVal.getValueType() == MVT::i32);
|
|
MVT::ValueType vt = Op.getValueType();
|
|
assert(vt == MVT::f32 ||
|
|
vt == MVT::f64);
|
|
|
|
SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal);
|
|
ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FSITOS : ARMISD::FSITOD;
|
|
return DAG.getNode(op, vt, Tmp);
|
|
}
|
|
|
|
static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
|
|
assert(Op.getValueType() == MVT::i32);
|
|
SDOperand FloatVal = Op.getOperand(0);
|
|
MVT::ValueType vt = FloatVal.getValueType();
|
|
assert(vt == MVT::f32 || vt == MVT::f64);
|
|
|
|
ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FTOSIS : ARMISD::FTOSID;
|
|
SDOperand Tmp = DAG.getNode(op, MVT::f32, FloatVal);
|
|
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Tmp);
|
|
}
|
|
|
|
static SDOperand LowerUINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
|
|
SDOperand IntVal = Op.getOperand(0);
|
|
assert(IntVal.getValueType() == MVT::i32);
|
|
MVT::ValueType vt = Op.getValueType();
|
|
assert(vt == MVT::f32 ||
|
|
vt == MVT::f64);
|
|
|
|
SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal);
|
|
ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FUITOS : ARMISD::FUITOD;
|
|
return DAG.getNode(op, vt, Tmp);
|
|
}
|
|
|
|
static SDOperand LowerFP_TO_UINT(SDOperand Op, SelectionDAG &DAG) {
|
|
assert(Op.getValueType() == MVT::i32);
|
|
SDOperand FloatVal = Op.getOperand(0);
|
|
MVT::ValueType vt = FloatVal.getValueType();
|
|
assert(vt == MVT::f32 || vt == MVT::f64);
|
|
|
|
ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FTOUIS : ARMISD::FTOUID;
|
|
SDOperand Tmp = DAG.getNode(op, MVT::f32, FloatVal);
|
|
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Tmp);
|
|
}
|
|
|
|
SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
|
switch (Op.getOpcode()) {
|
|
default:
|
|
assert(0 && "Should not custom lower this!");
|
|
abort();
|
|
case ISD::ConstantPool:
|
|
return LowerConstantPool(Op, DAG);
|
|
case ISD::GlobalAddress:
|
|
return LowerGlobalAddress(Op, DAG);
|
|
case ISD::FP_TO_SINT:
|
|
return LowerFP_TO_SINT(Op, DAG);
|
|
case ISD::SINT_TO_FP:
|
|
return LowerSINT_TO_FP(Op, DAG);
|
|
case ISD::FP_TO_UINT:
|
|
return LowerFP_TO_UINT(Op, DAG);
|
|
case ISD::UINT_TO_FP:
|
|
return LowerUINT_TO_FP(Op, DAG);
|
|
case ISD::FORMAL_ARGUMENTS:
|
|
return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
|
|
case ISD::CALL:
|
|
return LowerCALL(Op, DAG);
|
|
case ISD::RET:
|
|
return LowerRET(Op, DAG);
|
|
case ISD::SELECT_CC:
|
|
return LowerSELECT_CC(Op, DAG);
|
|
case ISD::BR_CC:
|
|
return LowerBR_CC(Op, DAG);
|
|
case ISD::VASTART:
|
|
return LowerVASTART(Op, DAG, VarArgsFrameIndex);
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Selector Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
/// ARMDAGToDAGISel - ARM specific code to select ARM machine
|
|
/// instructions for SelectionDAG operations.
|
|
///
|
|
namespace {
|
|
class ARMDAGToDAGISel : public SelectionDAGISel {
|
|
ARMTargetLowering Lowering;
|
|
|
|
public:
|
|
ARMDAGToDAGISel(TargetMachine &TM)
|
|
: SelectionDAGISel(Lowering), Lowering(TM) {
|
|
}
|
|
|
|
SDNode *Select(SDOperand Op);
|
|
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
|
|
bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
|
|
bool SelectAddrMode1(SDOperand N, SDOperand &Arg, SDOperand &Shift,
|
|
SDOperand &ShiftType);
|
|
bool SelectAddrMode5(SDOperand N, SDOperand &Arg, SDOperand &Offset);
|
|
|
|
// Include the pieces autogenerated from the target description.
|
|
#include "ARMGenDAGISel.inc"
|
|
};
|
|
|
|
void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
|
|
DEBUG(BB->dump());
|
|
|
|
DAG.setRoot(SelectRoot(DAG.getRoot()));
|
|
DAG.RemoveDeadNodes();
|
|
|
|
ScheduleAndEmitDAG(DAG);
|
|
}
|
|
|
|
static bool isInt12Immediate(SDNode *N, short &Imm) {
|
|
if (N->getOpcode() != ISD::Constant)
|
|
return false;
|
|
|
|
int32_t t = cast<ConstantSDNode>(N)->getValue();
|
|
int max = 1<<12;
|
|
int min = -max;
|
|
if (t > min && t < max) {
|
|
Imm = t;
|
|
return true;
|
|
}
|
|
else
|
|
return false;
|
|
}
|
|
|
|
static bool isInt12Immediate(SDOperand Op, short &Imm) {
|
|
return isInt12Immediate(Op.Val, Imm);
|
|
}
|
|
|
|
static uint32_t rotateL(uint32_t x) {
|
|
uint32_t bit31 = (x & (1 << 31)) >> 31;
|
|
uint32_t t = x << 1;
|
|
return t | bit31;
|
|
}
|
|
|
|
static bool isUInt8Immediate(uint32_t x) {
|
|
return x < (1 << 8);
|
|
}
|
|
|
|
static bool isRotInt8Immediate(uint32_t x) {
|
|
int r;
|
|
for (r = 0; r < 16; r++) {
|
|
if (isUInt8Immediate(x))
|
|
return true;
|
|
x = rotateL(rotateL(x));
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
|
|
SDOperand &Arg,
|
|
SDOperand &Shift,
|
|
SDOperand &ShiftType) {
|
|
switch(N.getOpcode()) {
|
|
case ISD::Constant: {
|
|
uint32_t val = cast<ConstantSDNode>(N)->getValue();
|
|
if(!isRotInt8Immediate(val)) {
|
|
Constant *C = ConstantInt::get(Type::UIntTy, val);
|
|
int alignment = 2;
|
|
SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment);
|
|
SDOperand Z = CurDAG->getTargetConstant(0, MVT::i32);
|
|
SDNode *n = CurDAG->getTargetNode(ARM::ldr, MVT::i32, Z, Addr);
|
|
Arg = SDOperand(n, 0);
|
|
} else
|
|
Arg = CurDAG->getTargetConstant(val, MVT::i32);
|
|
|
|
Shift = CurDAG->getTargetConstant(0, MVT::i32);
|
|
ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
|
|
return true;
|
|
}
|
|
case ISD::SRA:
|
|
Arg = N.getOperand(0);
|
|
Shift = N.getOperand(1);
|
|
ShiftType = CurDAG->getTargetConstant(ARMShift::ASR, MVT::i32);
|
|
return true;
|
|
case ISD::SRL:
|
|
Arg = N.getOperand(0);
|
|
Shift = N.getOperand(1);
|
|
ShiftType = CurDAG->getTargetConstant(ARMShift::LSR, MVT::i32);
|
|
return true;
|
|
case ISD::SHL:
|
|
Arg = N.getOperand(0);
|
|
Shift = N.getOperand(1);
|
|
ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
Arg = N;
|
|
Shift = CurDAG->getTargetConstant(0, MVT::i32);
|
|
ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand N, SDOperand &Arg,
|
|
SDOperand &Offset) {
|
|
//TODO: detect offset
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
Arg = N;
|
|
return true;
|
|
}
|
|
|
|
//register plus/minus 12 bit offset
|
|
bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
|
|
SDOperand &Base) {
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
if (N.getOpcode() == ISD::ADD) {
|
|
short imm = 0;
|
|
if (isInt12Immediate(N.getOperand(1), imm)) {
|
|
Offset = CurDAG->getTargetConstant(imm, MVT::i32);
|
|
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
|
|
Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
|
|
} else {
|
|
Base = N.getOperand(0);
|
|
}
|
|
return true; // [r+i]
|
|
}
|
|
}
|
|
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
|
|
Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
|
|
}
|
|
else
|
|
Base = N;
|
|
return true; //any address fits in a register
|
|
}
|
|
|
|
SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
|
|
SDNode *N = Op.Val;
|
|
|
|
switch (N->getOpcode()) {
|
|
default:
|
|
return SelectCode(Op);
|
|
break;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
} // end anonymous namespace
|
|
|
|
/// createARMISelDag - This pass converts a legalized DAG into a
|
|
/// ARM-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
|
|
return new ARMDAGToDAGISel(TM);
|
|
}
|