llvm-6502/test/MC/Mips/set-mips-directives.s
Daniel Sanders 98b419bff7 [mips] Add assembler support for '.set mipsX'.
Summary:
This patch also fixes an issue with the way the Mips assembler enables/disables architecture
features. Before this patch, the assembler never disabled feature bits. For example,
.set mips64
.set mips32r2

would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right.
Unfortunately this isn't trivial to fix because there's not an easy way to clear
feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits
that imply the feature being cleared and not the implied bits by the feature (there's a
better explanation to the code I added).

Patch by Matheus Almeida and updated by Toma Tabacu

Reviewers: vmedic, matheusalmeida, dsanders

Reviewed By: dsanders

Subscribers: tomatabacu, llvm-commits

Differential Revision: http://reviews.llvm.org/D4123


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214709 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-04 12:20:00 +00:00

52 lines
1.1 KiB
ArmAsm

# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips1 | \
# RUN: FileCheck %s
.text
.set noreorder
.set mips1
add $2, $2, $2
.set mips2
ll $2,-2($2)
.set mips3
dadd $2,$2,$2
.set mips4
ldxc1 $f8,$2($4)
.set mips5
luxc1 $f19,$2($4)
.set mips32
clo $2,$2
.set mips32r2
rotr $2,15
.set mips32r6
mod $2, $4, $6
.set mips64
daddi $2, $2, 10
.set mips64r2
drotr32 $1,$14,15
.set mips64r6
mod $2, $4, $6
# CHECK: .set noreorder
# CHECK: .set mips1
# CHECK: add $2, $2, $2
# CHECK: .set mips2
# CHECK: ll $2, -2($2)
# CHECK: .set mips3
# CHECK: dadd $2, $2, $2
# CHECK: .set mips4
# CHECK: ldxc1 $f8, $2($4)
# CHECK: .set mips5
# CHECK: luxc1 $f19, $2($4)
# CHECK: .set mips32
# CHECK: clo $2, $2
# CHECK: .set mips32r2
# CHECK: rotr $2, $2, 15
# CHECK: .set mips32r6
# CHECK: mod $2, $4, $6
# CHECK: .set mips64
# CHECK: daddi $2, $2, 10
# CHECK: .set mips64r2
# CHECK: drotr32 $1, $14, 15
# CHECK: .set mips64r6
# CHECK: mod $2, $4, $6