mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-19 01:13:25 +00:00
c9f5f3f64f
This eliminates the need for several awkward casts, including the last dynamic_cast under lib/Target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
4.6 KiB
C++
113 lines
4.6 KiB
C++
//===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the Sparc implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef SPARCINSTRUCTIONINFO_H
|
|
#define SPARCINSTRUCTIONINFO_H
|
|
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
|
#include "SparcRegisterInfo.h"
|
|
|
|
namespace llvm {
|
|
|
|
/// SPII - This namespace holds all of the target specific flags that
|
|
/// instruction info tracks.
|
|
///
|
|
namespace SPII {
|
|
enum {
|
|
Pseudo = (1<<0),
|
|
Load = (1<<1),
|
|
Store = (1<<2),
|
|
DelaySlot = (1<<3)
|
|
};
|
|
}
|
|
|
|
class SparcInstrInfo : public TargetInstrInfoImpl {
|
|
const SparcRegisterInfo RI;
|
|
const SparcSubtarget& Subtarget;
|
|
public:
|
|
explicit SparcInstrInfo(SparcSubtarget &ST);
|
|
|
|
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
|
/// such, whenever a client has an instance of instruction info, it should
|
|
/// always be able to get register info as well (through this method).
|
|
///
|
|
virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; }
|
|
|
|
/// Return true if the instruction is a register to register move and
|
|
/// leave the source and dest operands in the passed parameters.
|
|
///
|
|
virtual bool isMoveInstr(const MachineInstr &MI,
|
|
unsigned &SrcReg, unsigned &DstReg) const;
|
|
|
|
/// isLoadFromStackSlot - If the specified machine instruction is a direct
|
|
/// load from a stack slot, return the virtual or physical register number of
|
|
/// the destination along with the FrameIndex of the loaded stack slot. If
|
|
/// not, return 0. This predicate must return 0 if the instruction has
|
|
/// any side effects other than loading from the stack slot.
|
|
virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
|
|
|
|
/// isStoreToStackSlot - If the specified machine instruction is a direct
|
|
/// store to a stack slot, return the virtual or physical register number of
|
|
/// the source reg along with the FrameIndex of the loaded stack slot. If
|
|
/// not, return 0. This predicate must return 0 if the instruction has
|
|
/// any side effects other than storing to the stack slot.
|
|
virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
|
|
|
|
|
|
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB,
|
|
const std::vector<MachineOperand> &Cond) const;
|
|
|
|
virtual void copyRegToReg(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned DestReg, unsigned SrcReg,
|
|
const TargetRegisterClass *DestRC,
|
|
const TargetRegisterClass *SrcRC) const;
|
|
|
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
const TargetRegisterClass *RC) const;
|
|
|
|
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
const TargetRegisterClass *RC,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
|
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
unsigned DestReg, int FrameIndex,
|
|
const TargetRegisterClass *RC) const;
|
|
|
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
const TargetRegisterClass *RC,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
|
|
virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
|
|
MachineInstr* MI,
|
|
SmallVectorImpl<unsigned> &Ops,
|
|
int FrameIndex) const;
|
|
|
|
virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
|
|
MachineInstr* MI,
|
|
SmallVectorImpl<unsigned> &Ops,
|
|
MachineInstr* LoadMI) const {
|
|
return 0;
|
|
}
|
|
};
|
|
|
|
}
|
|
|
|
#endif
|