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https://github.com/c64scene-ar/llvm-6502.git
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3eff16e27a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78456 91177308-0d34-0410-b5e6-96231b3b80d8
214 lines
7.1 KiB
C++
214 lines
7.1 KiB
C++
//===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "t2-reduce-size"
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#include "ARM.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMBaseInstrInfo.h"
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#include "Thumb2InstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(NumNarrows, "Number of 32-bit instructions reduced to 16-bit ones");
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STATISTIC(Num2Addrs, "Number of 32-bit instructions reduced to 2-address");
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namespace {
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/// ReduceTable - A static table with information on mapping from wide
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/// opcodes to narrow
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struct ReduceEntry {
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unsigned WideOpc; // Wide opcode
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unsigned NarrowOpc1; // Narrow opcode to transform to
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unsigned NarrowOpc2; // Narrow opcode when it's two-address
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uint8_t Imm1Limit; // Limit of immediate field (bits)
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uint8_t Imm2Limit; // Limit of immediate field when it's two-address
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unsigned LowRegs1 : 1; // Only possible if low-registers are used
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unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
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unsigned PredCC : 1; // 0 - If predicated, cc is on and vice versa.
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// 1 - No cc field.
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unsigned Special : 1; // Needs to be dealt with specially
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};
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static const ReduceEntry ReduceTable[] = {
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// Wide, Narrow1, Narrow2, mm1, imm2, lo1, lo2, P/C, S
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{ ARM::t2ADCrr, ARM::tADC, 0, 0, 0, 1, 0, 0, 0 },
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{ ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0, 0 },
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{ ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 1, 0 },
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{ ARM::t2ANDrr, ARM::tAND, 0, 0, 0, 1, 0, 0, 0 },
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{ ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 1, 0, 0 },
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{ ARM::t2ASRrr, ARM::tASRrr, 0, 0, 0, 1, 0, 0, 0 },
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{ ARM::t2BICrr, ARM::tBIC, 0, 0, 0, 1, 0, 0, 0 },
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{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 1, 0 }
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};
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class VISIBILITY_HIDDEN Thumb2SizeReduce : public MachineFunctionPass {
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public:
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static char ID;
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Thumb2SizeReduce();
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const TargetInstrInfo *TII;
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "Thumb2 instruction size reduction pass";
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}
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private:
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/// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
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DenseMap<unsigned, unsigned> ReduceOpcodeMap;
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/// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
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/// instruction.
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bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr &MI,
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const ReduceEntry &Entry);
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/// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
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/// non-two-address instruction.
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bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr &MI,
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const ReduceEntry &Entry);
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/// ReduceMBB - Reduce width of instructions in the specified basic block.
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bool ReduceMBB(MachineBasicBlock &MBB);
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};
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char Thumb2SizeReduce::ID = 0;
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}
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Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(&ID) {
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for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
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unsigned FromOpc = ReduceTable[i].WideOpc;
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if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
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assert(false && "Duplicated entries?");
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}
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}
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bool
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Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr &MI,
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const ReduceEntry &Entry) {
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const TargetInstrDesc &TID = MI.getDesc();
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unsigned Reg0 = MI.getOperand(0).getReg();
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unsigned Reg1 = MI.getOperand(1).getReg();
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if (Reg0 != Reg1)
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return false;
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if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
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return false;
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if (Entry.Imm2Limit) {
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unsigned Imm = MI.getOperand(2).getImm();
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unsigned Limit = (1 << Entry.Imm2Limit) - 1;
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if (Imm > Limit)
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return false;
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} else {
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unsigned Reg2 = MI.getOperand(2).getReg();
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if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
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return false;
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}
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// Most thumb1 instructions either can be predicated or set CPSR.
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bool HasCC = false;
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if (TID.hasOptionalDef()) {
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unsigned NumOps = TID.getNumOperands();
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HasCC = (MI.getOperand(NumOps-1).getReg() == ARM::CPSR);
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}
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
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if (Entry.PredCC == 0) {
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if (Pred == ARMCC::AL) {
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// Not predicated, must set CPSR.
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if (!HasCC) return false;
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} else {
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// Predicated, must not set CPSR.
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if (HasCC) return false;
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}
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} else {
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if (HasCC) return false;
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}
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// Add the 16-bit instruction.
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DebugLoc dl = MI.getDebugLoc();
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MachineInstrBuilder MIB =
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BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc2), Reg0).addReg(Reg0);
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if (HasCC)
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AddDefaultT1CC(MIB);
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MIB.addOperand(MI.getOperand(2)).addImm(Pred).addReg(PredReg);
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// Transfer implicit operands.
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for (unsigned i = TID.getNumOperands(), e = MI.getNumOperands(); i != e; ++i)
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MIB.addOperand(MI.getOperand(i));
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DOUT << "Converted 32-bit: " << MI << " to 16-bit: " << *MIB;
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MBB.erase(MI);
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++Num2Addrs;
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++NumNarrows;
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return true;
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}
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bool
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Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr &MI,
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const ReduceEntry &Entry) {
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return false;
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}
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bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
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MachineBasicBlock::iterator NextMII = next(MII);
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for (; MII != E; MII = NextMII) {
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NextMII = next(MII);
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MachineInstr &MI = *MII;
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unsigned Opcode = MI.getOpcode();
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DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
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if (OPI == ReduceOpcodeMap.end())
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continue;
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const ReduceEntry &Entry = ReduceTable[OPI->second];
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// Ignore "special" cases for now.
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if (Entry.Special)
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continue;
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// Try to transform to a 16-bit two-address instruction.
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if (Entry.NarrowOpc2 && ReduceTo2Addr(MBB, MI, Entry)) {
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Modified = true;
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continue;
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}
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// Try to transform ro a 16-bit non-two-address instruction.
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if (ReduceToNarrow(MBB, MI, Entry)) {
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Modified = true;
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continue;
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}
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}
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return Modified;
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}
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bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
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const TargetMachine &TM = MF.getTarget();
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TII = TM.getInstrInfo();
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bool Modified = false;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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Modified |= ReduceMBB(*I);
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return Modified;
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}
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/// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
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/// reduction pass.
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FunctionPass *llvm::createThumb2SizeReductionPass() {
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return new Thumb2SizeReduce();
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}
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