Tilmann Scheller 3b3fa38731 [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRB/LDRSB instructions. ... The ARM ARM prohibits LDRB/LDRSB instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214500 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-01 12:08:04 +00:00
..
Analysis
Assembler	verify-uselistorder: Change the default -num-shuffles=5	2014-07-31 18:46:24 +00:00
Bindings
Bitcode	verify-uselistorder: Change the default -num-shuffles=5	2014-07-31 18:46:24 +00:00
BugPoint
CodeGen	[mips][PR19612] Fix va_arg for big-endian mode.	2014-08-01 09:17:39 +00:00
DebugInfo
ExecutionEngine
Feature
FileCheck
Instrumentation	[msan] Fix handling of array types.	2014-07-31 11:02:27 +00:00
Integer
JitListener
Linker
LTO
MC	[ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRB/LDRSB instructions.	2014-08-01 12:08:04 +00:00
Object
Other
TableGen
tools	llvm-profdata: Add a test for mismatched numbers of counters	2014-07-30 23:36:06 +00:00
Transforms	SLPVectorizer: improved scheduling algorithm.	2014-08-01 09:20:42 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
TestRunner.sh