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https://github.com/c64scene-ar/llvm-6502.git
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dd950096b9
- Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we need to ensure that i128 is 16-byte aligned in real life), and 128 zero- extends are supported. - New td file: SPU128InstrInfo.td: this is where all new i128 support should be put in the future. - Continue to hammer on i64 operations and test cases; ensure that the only remaining problem will be i64 mul. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61784 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
884 B
TableGen
23 lines
884 B
TableGen
//===--- SPU128InstrInfo.td - Cell SPU 128-bit operations -*- tablegen -*--===//
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//
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// Cell SPU 128-bit operations
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//
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// Primary author: Scott Michel (scottm@aero.org)
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//===----------------------------------------------------------------------===//
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// zext 32->128: Zero extend 32-bit to 128-bit
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def : Pat<(i128 (zext R32C:$rSrc)),
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(ROTQMBYIr128_zext_r32 R32C:$rSrc, 12)>;
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// zext 64->128: Zero extend 64-bit to 128-bit
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def : Pat<(i128 (zext R64C:$rSrc)),
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(ROTQMBYIr128_zext_r64 R64C:$rSrc, 8)>;
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// zext 16->128: Zero extend 16-bit to 128-bit
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def : Pat<(i128 (zext R16C:$rSrc)),
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(ROTQMBYIr128_zext_r32 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff)), 12)>;
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// zext 8->128: Zero extend 8-bit to 128-bit
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def : Pat<(i128 (zext R8C:$rSrc)),
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(ROTQMBYIr128_zext_r32 (ANDIi8i32 R8C:$rSrc, 0xf), 12)>;
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