mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
This commit updates the stackmap format to version 1 to indicate the reorganizaion of several fields. This was done in order to align stackmap entries to their natural alignment and to minimize padding. Fixes <rdar://problem/16005902> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205254 91177308-0d34-0410-b5e6-96231b3b80d8
469 lines
15 KiB
LLVM
469 lines
15 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -disable-fp-elim | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -disable-fp-elim | FileCheck --check-prefix=SSE %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -disable-fp-elim | FileCheck --check-prefix=AVX %s
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; Stackmap Header: no constants - 6 callsites
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; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
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; CHECK-NEXT: __LLVM_StackMaps:
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; Header
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 0
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; Num Functions
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; CHECK-NEXT: .long 8
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; Num Constants
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; CHECK-NEXT: .long 0
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; Num Callsites
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; CHECK-NEXT: .long 8
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; Functions and stack size
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; CHECK-NEXT: .quad _test
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; CHECK-NEXT: .quad 8
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; CHECK-NEXT: .quad _property_access1
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; CHECK-NEXT: .quad 8
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; CHECK-NEXT: .quad _property_access2
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; CHECK-NEXT: .quad 24
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; CHECK-NEXT: .quad _property_access3
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; CHECK-NEXT: .quad 24
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; CHECK-NEXT: .quad _anyreg_test1
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; CHECK-NEXT: .quad 56
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; CHECK-NEXT: .quad _anyreg_test2
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; CHECK-NEXT: .quad 56
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; CHECK-NEXT: .quad _patchpoint_spilldef
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; CHECK-NEXT: .quad 56
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; CHECK-NEXT: .quad _patchpoint_spillargs
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; CHECK-NEXT: .quad 88
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; No constants
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; Callsites
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; test
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; CHECK-LABEL: .long L{{.*}}-_test
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; CHECK-NEXT: .short 0
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; 3 locations
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; CHECK-NEXT: .short 3
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; Loc 0: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 2: Constant 3
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 3
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define i64 @test() nounwind ssp uwtable {
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entry:
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call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 15, i8* null, i32 2, i32 1, i32 2, i64 3)
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ret i64 0
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}
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; property access 1 - %obj is an anyreg call argument and should therefore be in a register
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; CHECK-LABEL: .long L{{.*}}-_property_access1
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
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entry:
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%f = inttoptr i64 12297829382473034410 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 15, i8* %f, i32 1, i8* %obj)
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ret i64 %ret
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}
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; property access 2 - %obj is an anyreg call argument and should therefore be in a register
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; CHECK-LABEL: .long L{{.*}}-_property_access2
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define i64 @property_access2() nounwind ssp uwtable {
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entry:
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%obj = alloca i64, align 8
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%f = inttoptr i64 12297829382473034410 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %f, i32 1, i64* %obj)
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ret i64 %ret
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}
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; property access 3 - %obj is a frame index
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; CHECK-LABEL: .long L{{.*}}-_property_access3
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Direct RBP - ofs
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 6
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; CHECK-NEXT: .long
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define i64 @property_access3() nounwind ssp uwtable {
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entry:
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%obj = alloca i64, align 8
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%f = inttoptr i64 12297829382473034410 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 15, i8* %f, i32 0, i64* %obj)
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ret i64 %ret
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}
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; anyreg_test1
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; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
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; CHECK-NEXT: .short 0
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; 14 locations
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; CHECK-NEXT: .short 14
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 2: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 3: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 4: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 5: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 6: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 7: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 8: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 9: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 10: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 11: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 12: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 13: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
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entry:
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%f = inttoptr i64 12297829382473034410 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 15, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
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ret i64 %ret
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}
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; anyreg_test2
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; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
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; CHECK-NEXT: .short 0
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; 14 locations
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; CHECK-NEXT: .short 14
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 2: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 3: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 4: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 5: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 6: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 7: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 8: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 9: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 10: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 11: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 12: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 13: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
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entry:
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%f = inttoptr i64 12297829382473034410 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
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ret i64 %ret
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}
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; Test spilling the return value of an anyregcc call.
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;
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; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
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;
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; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 3
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; Loc 0: Register (some register that will be spilled to the stack)
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Register RDI
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 5
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; CHECK-NEXT: .long 0
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; Loc 1: Register RSI
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 4
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; CHECK-NEXT: .long 0
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define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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%result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
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tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
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ret i64 %result
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}
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; Test spilling the arguments of an anyregcc call.
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;
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; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
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;
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; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 5
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; Loc 0: Return a register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 1: Arg0 in a Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 2: Arg1 in a Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; Loc 3: Arg2 spilled to RBP +
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 6
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; CHECK-NEXT: .long
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; Loc 4: Arg3 spilled to RBP +
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 6
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; CHECK-NEXT: .long
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define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
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%result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
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ret i64 %result
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}
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; Make sure all regs are spilled
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define anyregcc void @anyregcc1() {
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entry:
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;SSE-LABEL: anyregcc1
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;SSE: pushq %rbp
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;SSE: pushq %rax
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;SSE: pushq %r15
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;SSE: pushq %r14
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;SSE: pushq %r13
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;SSE: pushq %r12
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;SSE: pushq %r11
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;SSE: pushq %r10
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;SSE: pushq %r9
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;SSE: pushq %r8
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;SSE: pushq %rdi
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;SSE: pushq %rsi
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;SSE: pushq %rdx
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;SSE: pushq %rcx
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;SSE: pushq %rbx
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;SSE: movaps %xmm15
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;SSE-NEXT: movaps %xmm14
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;SSE-NEXT: movaps %xmm13
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;SSE-NEXT: movaps %xmm12
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;SSE-NEXT: movaps %xmm11
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;SSE-NEXT: movaps %xmm10
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;SSE-NEXT: movaps %xmm9
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;SSE-NEXT: movaps %xmm8
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;SSE-NEXT: movaps %xmm7
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;SSE-NEXT: movaps %xmm6
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;SSE-NEXT: movaps %xmm5
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;SSE-NEXT: movaps %xmm4
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;SSE-NEXT: movaps %xmm3
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;SSE-NEXT: movaps %xmm2
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;SSE-NEXT: movaps %xmm1
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;SSE-NEXT: movaps %xmm0
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;AVX-LABEL:anyregcc1
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;AVX: pushq %rbp
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;AVX: pushq %rax
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;AVX: pushq %r15
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;AVX: pushq %r14
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;AVX: pushq %r13
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;AVX: pushq %r12
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;AVX: pushq %r11
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;AVX: pushq %r10
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;AVX: pushq %r9
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;AVX: pushq %r8
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;AVX: pushq %rdi
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;AVX: pushq %rsi
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;AVX: pushq %rdx
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;AVX: pushq %rcx
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;AVX: pushq %rbx
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;AVX: vmovaps %ymm15
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|
;AVX-NEXT: vmovaps %ymm14
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|
;AVX-NEXT: vmovaps %ymm13
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|
;AVX-NEXT: vmovaps %ymm12
|
|
;AVX-NEXT: vmovaps %ymm11
|
|
;AVX-NEXT: vmovaps %ymm10
|
|
;AVX-NEXT: vmovaps %ymm9
|
|
;AVX-NEXT: vmovaps %ymm8
|
|
;AVX-NEXT: vmovaps %ymm7
|
|
;AVX-NEXT: vmovaps %ymm6
|
|
;AVX-NEXT: vmovaps %ymm5
|
|
;AVX-NEXT: vmovaps %ymm4
|
|
;AVX-NEXT: vmovaps %ymm3
|
|
;AVX-NEXT: vmovaps %ymm2
|
|
;AVX-NEXT: vmovaps %ymm1
|
|
;AVX-NEXT: vmovaps %ymm0
|
|
call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{rbp},~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15}"()
|
|
ret void
|
|
}
|
|
|
|
; Make sure we don't spill any XMMs/YMMs
|
|
declare anyregcc void @foo()
|
|
define void @anyregcc2() {
|
|
entry:
|
|
;SSE-LABEL: anyregcc2
|
|
;SSE-NOT: movaps %xmm
|
|
;AVX-LABEL: anyregcc2
|
|
;AVX-NOT: vmovups %ymm
|
|
%a0 = call <2 x double> asm sideeffect "", "={xmm0}"() nounwind
|
|
%a1 = call <2 x double> asm sideeffect "", "={xmm1}"() nounwind
|
|
%a2 = call <2 x double> asm sideeffect "", "={xmm2}"() nounwind
|
|
%a3 = call <2 x double> asm sideeffect "", "={xmm3}"() nounwind
|
|
%a4 = call <2 x double> asm sideeffect "", "={xmm4}"() nounwind
|
|
%a5 = call <2 x double> asm sideeffect "", "={xmm5}"() nounwind
|
|
%a6 = call <2 x double> asm sideeffect "", "={xmm6}"() nounwind
|
|
%a7 = call <2 x double> asm sideeffect "", "={xmm7}"() nounwind
|
|
%a8 = call <2 x double> asm sideeffect "", "={xmm8}"() nounwind
|
|
%a9 = call <2 x double> asm sideeffect "", "={xmm9}"() nounwind
|
|
%a10 = call <2 x double> asm sideeffect "", "={xmm10}"() nounwind
|
|
%a11 = call <2 x double> asm sideeffect "", "={xmm11}"() nounwind
|
|
%a12 = call <2 x double> asm sideeffect "", "={xmm12}"() nounwind
|
|
%a13 = call <2 x double> asm sideeffect "", "={xmm13}"() nounwind
|
|
%a14 = call <2 x double> asm sideeffect "", "={xmm14}"() nounwind
|
|
%a15 = call <2 x double> asm sideeffect "", "={xmm15}"() nounwind
|
|
call anyregcc void @foo()
|
|
call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},{xmm8},{xmm9},{xmm10},{xmm11},{xmm12},{xmm13},{xmm14},{xmm15}"(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> %a3, <2 x double> %a4, <2 x double> %a5, <2 x double> %a6, <2 x double> %a7, <2 x double> %a8, <2 x double> %a9, <2 x double> %a10, <2 x double> %a11, <2 x double> %a12, <2 x double> %a13, <2 x double> %a14, <2 x double> %a15)
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
|
|
declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
|