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https://github.com/c64scene-ar/llvm-6502.git
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84149460d5
The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support boolean values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133873 91177308-0d34-0410-b5e6-96231b3b80d8
369 lines
12 KiB
C++
369 lines
12 KiB
C++
//===-- PTXISelLowering.cpp - PTX DAG Lowering Implementation -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the PTXTargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "PTX.h"
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#include "PTXISelLowering.h"
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#include "PTXMachineFunctionInfo.h"
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#include "PTXRegisterInfo.h"
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#include "PTXSubtarget.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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#include "PTXGenCallingConv.inc"
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//===----------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===----------------------------------------------------------------------===//
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PTXTargetLowering::PTXTargetLowering(TargetMachine &TM)
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: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
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// Set up the register classes.
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addRegisterClass(MVT::i1, PTX::RegPredRegisterClass);
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addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
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addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
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addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
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addRegisterClass(MVT::f32, PTX::RegF32RegisterClass);
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addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
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setBooleanContents(ZeroOrOneBooleanContent);
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setMinFunctionAlignment(2);
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////////////////////////////////////
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/////////// Expansion //////////////
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////////////////////////////////////
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// (any/zero/sign) extload => load + (any/zero/sign) extend
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setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
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// f32 extload => load + fextend
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
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// f64 truncstore => trunc + store
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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// sign_extend_inreg => sign_extend
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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// br_cc => brcond
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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// select_cc => setcc
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
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////////////////////////////////////
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//////////// Legal /////////////////
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////////////////////////////////////
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setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
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setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
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////////////////////////////////////
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//////////// Custom ////////////////
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////////////////////////////////////
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// customise setcc to use bitwise logic if possible
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setOperationAction(ISD::SETCC, MVT::i1, Custom);
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// customize translation of memory addresses
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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// Compute derived properties from the register classes
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computeRegisterProperties();
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}
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MVT::SimpleValueType PTXTargetLowering::getSetCCResultType(EVT VT) const {
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return MVT::i1;
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}
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SDValue PTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default:
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llvm_unreachable("Unimplemented operand");
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case ISD::SETCC:
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return LowerSETCC(Op, DAG);
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case ISD::GlobalAddress:
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return LowerGlobalAddress(Op, DAG);
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}
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}
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const char *PTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default:
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llvm_unreachable("Unknown opcode");
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case PTXISD::COPY_ADDRESS:
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return "PTXISD::COPY_ADDRESS";
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case PTXISD::LOAD_PARAM:
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return "PTXISD::LOAD_PARAM";
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case PTXISD::STORE_PARAM:
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return "PTXISD::STORE_PARAM";
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case PTXISD::EXIT:
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return "PTXISD::EXIT";
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case PTXISD::RET:
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return "PTXISD::RET";
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}
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}
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//===----------------------------------------------------------------------===//
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// Custom Lower Operation
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//===----------------------------------------------------------------------===//
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SDValue PTXTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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assert(Op.getValueType() == MVT::i1 && "SetCC type must be 1-bit integer");
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SDValue Op0 = Op.getOperand(0);
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SDValue Op1 = Op.getOperand(1);
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SDValue Op2 = Op.getOperand(2);
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DebugLoc dl = Op.getDebugLoc();
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
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// Look for X == 0, X == 1, X != 0, or X != 1
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// We can simplify these to bitwise logic
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if (Op1.getOpcode() == ISD::Constant &&
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(cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
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cast<ConstantSDNode>(Op1)->isNullValue()) &&
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(CC == ISD::SETEQ || CC == ISD::SETNE)) {
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return DAG.getNode(ISD::AND, dl, MVT::i1, Op0, Op1);
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}
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return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2);
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}
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SDValue PTXTargetLowering::
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LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
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EVT PtrVT = getPointerTy();
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DebugLoc dl = Op.getDebugLoc();
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const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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assert(PtrVT.isSimple() && "Pointer must be to primitive type.");
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SDValue targetGlobal = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
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SDValue movInstr = DAG.getNode(PTXISD::COPY_ADDRESS,
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dl,
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PtrVT.getSimpleVT(),
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targetGlobal);
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return movInstr;
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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struct argmap_entry {
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MVT::SimpleValueType VT;
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TargetRegisterClass *RC;
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TargetRegisterClass::iterator loc;
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argmap_entry(MVT::SimpleValueType _VT, TargetRegisterClass *_RC)
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: VT(_VT), RC(_RC), loc(_RC->begin()) {}
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void reset() { loc = RC->begin(); }
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bool operator==(MVT::SimpleValueType _VT) const { return VT == _VT; }
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} argmap[] = {
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argmap_entry(MVT::i1, PTX::RegPredRegisterClass),
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argmap_entry(MVT::i16, PTX::RegI16RegisterClass),
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argmap_entry(MVT::i32, PTX::RegI32RegisterClass),
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argmap_entry(MVT::i64, PTX::RegI64RegisterClass),
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argmap_entry(MVT::f32, PTX::RegF32RegisterClass),
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argmap_entry(MVT::f64, PTX::RegF64RegisterClass)
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};
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} // end anonymous namespace
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SDValue PTXTargetLowering::
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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if (isVarArg) llvm_unreachable("PTX does not support varargs");
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MachineFunction &MF = DAG.getMachineFunction();
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const PTXSubtarget& ST = getTargetMachine().getSubtarget<PTXSubtarget>();
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PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
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switch (CallConv) {
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default:
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llvm_unreachable("Unsupported calling convention");
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break;
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case CallingConv::PTX_Kernel:
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MFI->setKernel(true);
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break;
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case CallingConv::PTX_Device:
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MFI->setKernel(false);
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break;
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}
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// We do one of two things here:
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// IsKernel || SM >= 2.0 -> Use param space for arguments
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// SM < 2.0 -> Use registers for arguments
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if (MFI->isKernel() || ST.useParamSpaceForDeviceArgs()) {
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// We just need to emit the proper LOAD_PARAM ISDs
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for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
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assert((!MFI->isKernel() || Ins[i].VT != MVT::i1) &&
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"Kernels cannot take pred operands");
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SDValue ArgValue = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain,
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DAG.getTargetConstant(i, MVT::i32));
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InVals.push_back(ArgValue);
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// Instead of storing a physical register in our argument list, we just
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// store the total size of the parameter, in bits. The ASM printer
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// knows how to process this.
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MFI->addArgReg(Ins[i].VT.getStoreSizeInBits());
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}
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}
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else {
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// For device functions, we use the PTX calling convention to do register
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// assignments then create CopyFromReg ISDs for the allocated registers
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), ArgLocs,
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*DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_PTX);
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign& VA = ArgLocs[i];
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EVT RegVT = VA.getLocVT();
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TargetRegisterClass* TRC = 0;
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assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
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// Determine which register class we need
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if (RegVT == MVT::i1) {
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TRC = PTX::RegPredRegisterClass;
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}
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else if (RegVT == MVT::i16) {
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TRC = PTX::RegI16RegisterClass;
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}
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else if (RegVT == MVT::i32) {
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TRC = PTX::RegI32RegisterClass;
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}
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else if (RegVT == MVT::i64) {
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TRC = PTX::RegI64RegisterClass;
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}
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else if (RegVT == MVT::f32) {
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TRC = PTX::RegF32RegisterClass;
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}
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else if (RegVT == MVT::f64) {
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TRC = PTX::RegF64RegisterClass;
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}
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else {
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llvm_unreachable("Unknown parameter type");
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}
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unsigned Reg = MF.getRegInfo().createVirtualRegister(TRC);
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MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
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SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
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InVals.push_back(ArgValue);
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MFI->addArgReg(VA.getLocReg());
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}
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}
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return Chain;
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}
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SDValue PTXTargetLowering::
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LowerReturn(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl,
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SelectionDAG &DAG) const {
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if (isVarArg) llvm_unreachable("PTX does not support varargs");
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switch (CallConv) {
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default:
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llvm_unreachable("Unsupported calling convention.");
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case CallingConv::PTX_Kernel:
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assert(Outs.size() == 0 && "Kernel must return void.");
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return DAG.getNode(PTXISD::EXIT, dl, MVT::Other, Chain);
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case CallingConv::PTX_Device:
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//assert(Outs.size() <= 1 && "Can at most return one value.");
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break;
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}
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MachineFunction& MF = DAG.getMachineFunction();
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PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
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SDValue Flag;
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// Even though we could use the .param space for return arguments for
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// device functions if SM >= 2.0 and the number of return arguments is
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// only 1, we just always use registers since this makes the codegen
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// easier.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), RVLocs, *DAG.getContext());
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CCInfo.AnalyzeReturn(Outs, RetCC_PTX);
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for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
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CCValAssign& VA = RVLocs[i];
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assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
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unsigned Reg = VA.getLocReg();
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DAG.getMachineFunction().getRegInfo().addLiveOut(Reg);
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Chain = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i], Flag);
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// Guarantee that all emitted copies are stuck together,
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// avoiding something bad
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Flag = Chain.getValue(1);
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MFI->addRetReg(Reg);
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}
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if (Flag.getNode() == 0) {
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return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain);
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}
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else {
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return DAG.getNode(PTXISD::RET, dl, MVT::Other, Chain, Flag);
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}
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}
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