llvm-6502/test/CodeGen/NVPTX/arithmetic-int.ll
Justin Holewinski 49683f3c96 This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.
The new target machines are:

nvptx (old ptx32) => 32-bit PTX
nvptx64 (old ptx64) => 64-bit PTX

The sources are based on the internal NVIDIA NVPTX back-end, and
contain more functionality than the current PTX back-end currently
provides.

NV_CONTRIB

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04 20:18:50 +00:00

296 lines
6.4 KiB
LLVM

; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
;; These tests should run for all targets
;;===-- Basic instruction selection tests ---------------------------------===;;
;;; i64
define i64 @add_i64(i64 %a, i64 %b) {
; CHECK: add.s64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %rl{{[0-9]+}}
; CHECK: ret
%ret = add i64 %a, %b
ret i64 %ret
}
define i64 @sub_i64(i64 %a, i64 %b) {
; CHECK: sub.s64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %rl{{[0-9]+}}
; CHECK: ret
%ret = sub i64 %a, %b
ret i64 %ret
}
define i64 @mul_i64(i64 %a, i64 %b) {
; CHECK: mul.lo.s64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %rl{{[0-9]+}}
; CHECK: ret
%ret = mul i64 %a, %b
ret i64 %ret
}
define i64 @sdiv_i64(i64 %a, i64 %b) {
; CHECK: div.s64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %rl{{[0-9]+}}
; CHECK: ret
%ret = sdiv i64 %a, %b
ret i64 %ret
}
define i64 @udiv_i64(i64 %a, i64 %b) {
; CHECK: div.u64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %rl{{[0-9]+}}
; CHECK: ret
%ret = udiv i64 %a, %b
ret i64 %ret
}
define i64 @srem_i64(i64 %a, i64 %b) {
; CHECK: rem.s64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %rl{{[0-9]+}}
; CHECK: ret
%ret = srem i64 %a, %b
ret i64 %ret
}
define i64 @urem_i64(i64 %a, i64 %b) {
; CHECK: rem.u64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %rl{{[0-9]+}}
; CHECK: ret
%ret = urem i64 %a, %b
ret i64 %ret
}
define i64 @and_i64(i64 %a, i64 %b) {
; CHECK: and.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %rl{{[0-9]+}}
; CHECK: ret
%ret = and i64 %a, %b
ret i64 %ret
}
define i64 @or_i64(i64 %a, i64 %b) {
; CHECK: or.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %rl{{[0-9]+}}
; CHECK: ret
%ret = or i64 %a, %b
ret i64 %ret
}
define i64 @xor_i64(i64 %a, i64 %b) {
; CHECK: xor.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %rl{{[0-9]+}}
; CHECK: ret
%ret = xor i64 %a, %b
ret i64 %ret
}
define i64 @shl_i64(i64 %a, i64 %b) {
; PTX requires 32-bit shift amount
; CHECK: shl.b64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = shl i64 %a, %b
ret i64 %ret
}
define i64 @ashr_i64(i64 %a, i64 %b) {
; PTX requires 32-bit shift amount
; CHECK: shr.s64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = ashr i64 %a, %b
ret i64 %ret
}
define i64 @lshr_i64(i64 %a, i64 %b) {
; PTX requires 32-bit shift amount
; CHECK: shr.u64 %rl{{[0-9]+}}, %rl{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = lshr i64 %a, %b
ret i64 %ret
}
;;; i32
define i32 @add_i32(i32 %a, i32 %b) {
; CHECK: add.s32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = add i32 %a, %b
ret i32 %ret
}
define i32 @sub_i32(i32 %a, i32 %b) {
; CHECK: sub.s32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = sub i32 %a, %b
ret i32 %ret
}
define i32 @mul_i32(i32 %a, i32 %b) {
; CHECK: mul.lo.s32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = mul i32 %a, %b
ret i32 %ret
}
define i32 @sdiv_i32(i32 %a, i32 %b) {
; CHECK: div.s32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = sdiv i32 %a, %b
ret i32 %ret
}
define i32 @udiv_i32(i32 %a, i32 %b) {
; CHECK: div.u32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = udiv i32 %a, %b
ret i32 %ret
}
define i32 @srem_i32(i32 %a, i32 %b) {
; CHECK: rem.s32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = srem i32 %a, %b
ret i32 %ret
}
define i32 @urem_i32(i32 %a, i32 %b) {
; CHECK: rem.u32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = urem i32 %a, %b
ret i32 %ret
}
define i32 @and_i32(i32 %a, i32 %b) {
; CHECK: and.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = and i32 %a, %b
ret i32 %ret
}
define i32 @or_i32(i32 %a, i32 %b) {
; CHECK: or.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = or i32 %a, %b
ret i32 %ret
}
define i32 @xor_i32(i32 %a, i32 %b) {
; CHECK: xor.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = xor i32 %a, %b
ret i32 %ret
}
define i32 @shl_i32(i32 %a, i32 %b) {
; CHECK: shl.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = shl i32 %a, %b
ret i32 %ret
}
define i32 @ashr_i32(i32 %a, i32 %b) {
; CHECK: shr.s32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = ashr i32 %a, %b
ret i32 %ret
}
define i32 @lshr_i32(i32 %a, i32 %b) {
; CHECK: shr.u32 %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = lshr i32 %a, %b
ret i32 %ret
}
;;; i16
define i16 @add_i16(i16 %a, i16 %b) {
; CHECK: add.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
; CHECK: ret
%ret = add i16 %a, %b
ret i16 %ret
}
define i16 @sub_i16(i16 %a, i16 %b) {
; CHECK: sub.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
; CHECK: ret
%ret = sub i16 %a, %b
ret i16 %ret
}
define i16 @mul_i16(i16 %a, i16 %b) {
; CHECK: mul.lo.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
; CHECK: ret
%ret = mul i16 %a, %b
ret i16 %ret
}
define i16 @sdiv_i16(i16 %a, i16 %b) {
; CHECK: div.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
; CHECK: ret
%ret = sdiv i16 %a, %b
ret i16 %ret
}
define i16 @udiv_i16(i16 %a, i16 %b) {
; CHECK: div.u16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
; CHECK: ret
%ret = udiv i16 %a, %b
ret i16 %ret
}
define i16 @srem_i16(i16 %a, i16 %b) {
; CHECK: rem.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
; CHECK: ret
%ret = srem i16 %a, %b
ret i16 %ret
}
define i16 @urem_i16(i16 %a, i16 %b) {
; CHECK: rem.u16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
; CHECK: ret
%ret = urem i16 %a, %b
ret i16 %ret
}
define i16 @and_i16(i16 %a, i16 %b) {
; CHECK: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
; CHECK: ret
%ret = and i16 %a, %b
ret i16 %ret
}
define i16 @or_i16(i16 %a, i16 %b) {
; CHECK: or.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
; CHECK: ret
%ret = or i16 %a, %b
ret i16 %ret
}
define i16 @xor_i16(i16 %a, i16 %b) {
; CHECK: xor.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %rs{{[0-9]+}}
; CHECK: ret
%ret = xor i16 %a, %b
ret i16 %ret
}
define i16 @shl_i16(i16 %a, i16 %b) {
; PTX requires 32-bit shift amount
; CHECK: shl.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = shl i16 %a, %b
ret i16 %ret
}
define i16 @ashr_i16(i16 %a, i16 %b) {
; PTX requires 32-bit shift amount
; CHECK: shr.s16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = ashr i16 %a, %b
ret i16 %ret
}
define i16 @lshr_i16(i16 %a, i16 %b) {
; PTX requires 32-bit shift amount
; CHECK: shr.u16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, %r{{[0-9]+}}
; CHECK: ret
%ret = lshr i16 %a, %b
ret i16 %ret
}