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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152581 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
1.6 KiB
C++
53 lines
1.6 KiB
C++
//===- DFAPacketizerEmitter.h - Packetization DFA for a VLIW machine-------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class parses the Schedule.td file and produces an API that can be used
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// to reason about whether an instruction can be added to a packet on a VLIW
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// architecture. The class internally generates a deterministic finite
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// automaton (DFA) that models all possible mappings of machine instructions
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// to functional units as instructions are added to a packet.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <map>
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#include <string>
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namespace llvm {
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//
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// class DFAGen: class that generates and prints out the DFA for resource
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// tracking.
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//
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class DFAGen : public TableGenBackend {
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private:
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std::string TargetName;
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//
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// allInsnClasses is the set of all possible resources consumed by an
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// InstrStage.
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//
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DenseSet<unsigned> allInsnClasses;
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RecordKeeper &Records;
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public:
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DFAGen(RecordKeeper &R);
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//
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// collectAllInsnClasses: Populate allInsnClasses which is a set of units
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// used in each stage.
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//
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void collectAllInsnClasses(const std::string &Name,
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Record *ItinData,
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unsigned &NStages,
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raw_ostream &OS);
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void run(raw_ostream &OS);
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};
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}
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