Matt Arsenault ab2315014e R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32 ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226230 91177308-0d34-0410-b5e6-96231b3b80d8

2015-01-15 23:58:35 +00:00

..

AsmParser

R600/SI: Add a stub GCNTargetMachine

2015-01-06 18:00:21 +00:00

InstPrinter

[cleanup] Re-sort all the #include lines in LLVM using

2015-01-14 11:23:27 +00:00

MCTargetDesc

Revert "Add r224985 back with two fixes."

2015-01-14 19:07:23 +00:00

TargetInfo

R600/SI: Add a stub GCNTargetMachine

2015-01-06 18:00:21 +00:00

AMDGPU.h

R600/SI: Spill VGPRs to scratch space for compute shaders

2015-01-14 15:42:31 +00:00

AMDGPU.td

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AMDGPUAlwaysInlinePass.cpp

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AMDGPUAsmPrinter.cpp

R600/SI: Remove VReg_32 register class

2015-01-07 20:59:25 +00:00

AMDGPUAsmPrinter.h

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AMDGPUCallingConv.td

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AMDGPUFrameLowering.cpp

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AMDGPUFrameLowering.h

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AMDGPUInstrInfo.cpp

R600/SI: Don't shrink instructions whose e32 encoding doesn't exist

2015-01-15 18:42:51 +00:00

AMDGPUInstrInfo.h

R600/SI: Don't shrink instructions whose e32 encoding doesn't exist

2015-01-15 18:42:51 +00:00

AMDGPUInstrInfo.td

R600/SI: Add class intrinsic

2015-01-06 23:00:37 +00:00

AMDGPUInstructions.td

R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32

2015-01-15 23:58:35 +00:00

AMDGPUIntrinsicInfo.cpp

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AMDGPUIntrinsicInfo.h

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AMDGPUIntrinsics.td

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AMDGPUISelDAGToDAG.cpp

R600/SI: Use RegisterOperands to specify which operands can accept immediates

2015-01-12 19:33:18 +00:00

AMDGPUISelLowering.cpp

Implement new way of expanding extloads.

2015-01-14 01:35:17 +00:00

AMDGPUISelLowering.h

R600: Implement getRecipEstimate

2015-01-13 20:53:23 +00:00

AMDGPUMachineFunction.cpp

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AMDGPUMachineFunction.h

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AMDGPUMCInstLower.cpp

R600/SI: Don't shrink instructions whose e32 encoding doesn't exist

2015-01-15 18:42:51 +00:00

AMDGPUMCInstLower.h

R600/SI: Don't shrink instructions whose e32 encoding doesn't exist

2015-01-15 18:42:51 +00:00

AMDGPUPromoteAlloca.cpp

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AMDGPURegisterInfo.cpp

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AMDGPURegisterInfo.h

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AMDGPURegisterInfo.td

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AMDGPUSubtarget.cpp

[cleanup] Re-sort all the #include lines in LLVM using

2015-01-14 11:23:27 +00:00

AMDGPUSubtarget.h

[cleanup] Re-sort all the #include lines in LLVM using

2015-01-14 11:23:27 +00:00

AMDGPUTargetMachine.cpp

R600/SI: Spill VGPRs to scratch space for compute shaders

2015-01-14 15:42:31 +00:00

AMDGPUTargetMachine.h

R600/SI: Add a stub GCNTargetMachine

2015-01-06 18:00:21 +00:00

AMDGPUTargetTransformInfo.cpp

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AMDILCFGStructurizer.cpp

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AMDKernelCodeT.h

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CaymanInstructions.td

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CIInstructions.td

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CMakeLists.txt

R600/SI: Spill VGPRs to scratch space for compute shaders

2015-01-14 15:42:31 +00:00

EvergreenInstructions.td

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LLVMBuild.txt

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Makefile

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Processors.td

R600/SI: Define a schedule model

2015-01-14 01:13:19 +00:00

R600ClauseMergePass.cpp

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R600ControlFlowFinalizer.cpp

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R600Defines.h

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R600EmitClauseMarkers.cpp

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R600ExpandSpecialInstrs.cpp

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R600InstrFormats.td

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R600InstrInfo.cpp

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R600InstrInfo.h

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R600Instructions.td

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R600Intrinsics.td

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R600ISelLowering.cpp

[SelectionDAG] Allow targets to specify legality of extloads' result

2015-01-08 00:51:32 +00:00

R600ISelLowering.h

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R600MachineFunctionInfo.cpp

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R600MachineFunctionInfo.h

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R600MachineScheduler.cpp

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R600MachineScheduler.h

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R600OptimizeVectorRegisters.cpp

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R600Packetizer.cpp

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R600RegisterInfo.cpp

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R600RegisterInfo.h

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R600RegisterInfo.td

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R600Schedule.td

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R600TextureIntrinsicsReplacer.cpp

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R700Instructions.td

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SIAnnotateControlFlow.cpp

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SIDefines.h

R600/SI: Use RegisterOperands to specify which operands can accept immediates

2015-01-12 19:33:18 +00:00

SIFixSGPRCopies.cpp

R600/SI: Remove VReg_32 register class

2015-01-07 20:59:25 +00:00

SIFixSGPRLiveRanges.cpp

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SIFoldOperands.cpp

R600/SI: Add pattern for bitcasting fp immediates to integers

2015-01-13 22:59:41 +00:00

SIInsertWaits.cpp

R600/SI: Insert s_waitcnt before s_barrier instructions.

2015-01-06 19:52:07 +00:00

SIInstrFormats.td

R600/SI: Add common class VOPAnyCommon

2015-01-15 18:42:44 +00:00

SIInstrInfo.cpp

R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VI

2015-01-15 18:43:01 +00:00

SIInstrInfo.h

R600/SI: Don't shrink instructions whose e32 encoding doesn't exist

2015-01-15 18:42:51 +00:00

SIInstrInfo.td

R600/SI: Fix trailing comma with modifiers

2015-01-15 23:17:03 +00:00

SIInstructions.td

R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32

2015-01-15 23:58:35 +00:00

SIIntrinsics.td

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SIISelLowering.cpp

R600/SI: Fix bad code with unaligned byte vector loads

2015-01-14 01:35:22 +00:00

SIISelLowering.h

R600/SI: Fix bad code with unaligned byte vector loads

2015-01-14 01:35:22 +00:00

SILoadStoreOptimizer.cpp

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SILowerControlFlow.cpp

R600/SI: Add pattern for bitcasting fp immediates to integers

2015-01-13 22:59:41 +00:00

SILowerI1Copies.cpp

R600/SI: Remove VReg_32 register class

2015-01-07 20:59:25 +00:00

SIMachineFunctionInfo.cpp

R600/SI: Spill VGPRs to scratch space for compute shaders

2015-01-14 15:42:31 +00:00

SIMachineFunctionInfo.h

R600/SI: Spill VGPRs to scratch space for compute shaders

2015-01-14 15:42:31 +00:00

SIPrepareScratchRegs.cpp

R600/SI: Spill VGPRs to scratch space for compute shaders

2015-01-14 15:42:31 +00:00

SIRegisterInfo.cpp

R600/SI: Spill VGPRs to scratch space for compute shaders

2015-01-14 15:42:31 +00:00

SIRegisterInfo.h

R600/SI: Spill VGPRs to scratch space for compute shaders

2015-01-14 15:42:31 +00:00

SIRegisterInfo.td

R600/SI: Use RegisterOperands to specify which operands can accept immediates

2015-01-12 19:33:18 +00:00

SISchedule.td

R600/SI: Define a schedule model

2015-01-14 01:13:19 +00:00

SIShrinkInstructions.cpp

R600/SI: Don't shrink instructions whose e32 encoding doesn't exist

2015-01-15 18:42:51 +00:00

SITypeRewriter.cpp

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VIInstrFormats.td

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VIInstructions.td

R600/SI: Unify VOP2 instructions which are VOP3-only on VI

2015-01-15 18:43:06 +00:00