mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-18 12:29:27 +00:00
2010b3eea6
Changed cout to DOUT, and TODOs to FIXMEs. Other changes as per coding conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51105 91177308-0d34-0410-b5e6-96231b3b80d8
303 lines
11 KiB
TableGen
303 lines
11 KiB
TableGen
//===- PIC16InstrInfo.td - PIC16 Register defs ----------------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "PIC16InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// PIC16 profiles and nodes
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// PIC16 addressing mode.
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//===----------------------------------------------------------------------===//
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// It matches address of globals as well as the stack slots
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// that are created for locals and temporaries. This addressing mode
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// converts the GlobalAddress and FrameIndex nodes to TargetGlobalAddress
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// and TargetFrameIndex nodes.
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def diraddrmode : ComplexPattern<i16, 2, "SelectDirectAM", [frameindex], []>;
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def dirloadmode : ComplexPattern<i16, 2, "LoadNothing", [frameindex], []>;
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def indirloadmode : ComplexPattern<i16, 2, "LoadFSR", [frameindex], []>;
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// Address operand.
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def mem : Operand<i16> {
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let PrintMethod = "printAddrModeOperand";
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let MIOperandInfo = (ops i16imm, PTRRegs);
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}
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// Instruction operand types
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def simm8 : Operand<i8>;
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// These are target-independent nodes, but have target-specific formats.
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def SDT_PIC16CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i8> ]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PIC16CallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PIC16CallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def PIC16Wrapper : SDNode<"PIC16ISD::Wrapper", SDTIntUnaryOp>;
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// so_imm_XFORM - Return a so_imm value packed into the format described for
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// so_imm def below.
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def so_imm_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant((int8_t)N->getValue(), MVT::i32);
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}]>;
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def so_imm : Operand<i8>,
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PatLeaf<(imm), [{}]> {
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let PrintMethod = "printSOImmOperand";
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}
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// PIC16 Address Mode! SDNode frameindex could possibily be a match
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// since load and store instructions from stack used it.
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def addr : Operand<i16>;
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// Arithmetic 2 register operands
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class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od> :
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LiteralFormat< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, " $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, Od:$c))]>;
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// Memory Load/Store.
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class LoadDirect<bits<6> op, string instr_asm, PatFrag OpNode>:
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ByteFormat< op,
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(outs CPURegs:$dst),
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(ins mem:$addr),
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!strconcat(instr_asm, " $addr"),
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[(set CPURegs:$dst, (OpNode diraddrmode:$addr))]>;
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class LoadInDirect<bits<6> op, string instr_asm, PatFrag OpNode>:
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ByteFormat< op,
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(outs PTRRegs:$dst),
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(ins mem:$addr),
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!strconcat(instr_asm, " $addr, $dst"),
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[(set PTRRegs:$dst, (OpNode indirloadmode:$addr))]>;
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class StoreDirect<bits<6> op, string instr_asm, PatFrag OpNode>:
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ByteFormat< op,
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(outs),
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(ins CPURegs:$src, mem:$addr),
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!strconcat(instr_asm, " $addr"),
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[(OpNode CPURegs:$src, diraddrmode:$addr)]>;
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class StoreInDirect<bits<6> op, string instr_asm, PatFrag OpNode>:
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ByteFormat< op,
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(outs),
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(ins CPURegs:$src, PTRRegs:$fsr),
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!strconcat(instr_asm, " $fsr"),
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[(OpNode CPURegs:$src, PTRRegs:$fsr)]>;
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// Move.
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class MovLit<bits<6> op, string instr_asm>:
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LiteralFormat< op,
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(outs CPURegs:$dst),
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(ins i8imm:$src),
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!strconcat(instr_asm, " $src"),
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[(set CPURegs:$dst, imm:$src)]>;
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// Arithmetic with memory store.
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// Arithmetic instrunctions involving W and memory location.
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// Since W is implicit, we only print the memory operand.
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class Arith1M<bits<6> op, string instr_asm, SDNode OpNode>:
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ByteFormat< op,
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(outs),
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(ins CPURegs:$b, mem:$dst),
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!strconcat(instr_asm, " $dst"),
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[(store (OpNode (load diraddrmode:$dst), CPURegs:$b), diraddrmode:$dst),
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(store (OpNode CPURegs:$b, (load diraddrmode:$dst)), diraddrmode:$dst)]>;
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// Arithmetic with memory load.
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// Arithmetic instrunctions involving W and memory location.
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// Since W is implicit, we only print the memory operand.
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class Arith1R<bits<6> op, string instr_asm, SDNode OpNode>:
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ByteFormat< op,
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(outs CPURegs:$dst),
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(ins mem:$src1, CPURegs:$src2),
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!strconcat(instr_asm, " $src1"),
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[(set CPURegs:$dst, (OpNode (load diraddrmode:$src1), CPURegs:$src2))]>;
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// Arithmetic with memory load.
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// Arithmetic instrunctions involving W and memory location.
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// Since W is implicit, we only print the memory operand.
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class Arith2R<bits<6> op, string instr_asm, SDNode OpNode>:
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ByteFormat< op,
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(outs CPURegs:$dst),
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(ins mem:$src1, CPURegs:$src2),
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!strconcat(instr_asm, " $src1"),
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[(set CPURegs:$dst, (OpNode CPURegs:$src2, (load diraddrmode:$src1)))]>;
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// PIC16I Instructions
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//===----------------------------------------------------------------------===//
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// Arithmetic
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// ADDiu just accept 16-bit immediates but we handle this on Pat's.
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// immZExt32 is used here so it can match GlobalAddress immediates.
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// def ADDLW : ArithI<0x09, "addlw", add, so_imm>;
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let isReMaterializable = 1 in {
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def MOVLW : MovLit<0x24, "movlw">;
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}
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// Load/Store
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def LFSR1 : LoadInDirect <0x4, "lfsr", load>;
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let isReMaterializable = 1 in {
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def MOVF : LoadDirect <0x23, "movf", load>;
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}
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def MOVWF : StoreDirect <0x2b, "movwf", store>;
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def MOVFSRINC : StoreInDirect <0x5, "movfsrinc", store>;
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def RETURN : ControlFormat<0x03, (outs), (ins), "return", []>;
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def ADDWF : Arith1M<0x01, "addwf", add>;
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def ADDFW : Arith1R<0x02, "addfw", add>;
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def ADDWFE : Arith1M<0x03, "addwfe", adde>;
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def ADDFWE : Arith1R<0x04, "addfwe", adde>;
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def ADDWFC : Arith1M<0x05, "addwfc", addc>;
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def ADDFWC : Arith1R<0x06, "addfwc", addc>;
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def SUBWF : Arith1M<0x07, "subwf", sub>;
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def SUBFW : Arith1R<0x08, "subfw", sub>;
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def SUBWFE : Arith1M<0x09, "subwfe", sube>;
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def SUBFWE : Arith1R<0x0a, "subfwe", sube>;
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def SUBWFC : Arith1M<0x0b, "subwfc", subc>;
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def SUBFWC : Arith1R<0x0d, "subfwc", subc>;
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def SUBRFW : Arith2R<0x08, "subfw", sub>;
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def SUBRFWE : Arith2R<0x0a, "subfwe", sube>;
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def SUBRFWC : Arith2R<0x0d, "subfwc", subc>;
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def brtarget : Operand<OtherVT>;
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class UncondJump< bits<4> op, string instr_asm>:
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BitFormat< op,
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(outs),
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(ins brtarget:$target),
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!strconcat(instr_asm, " $target"),
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[(br bb:$target)]>;
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def GOTO : UncondJump<0x1, "goto">;
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class LogicM<bits<6> op, string instr_asm, SDNode OpNode> :
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ByteFormat< op,
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(outs),
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(ins CPURegs:$b, mem:$dst),
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!strconcat(instr_asm, " $dst"),
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[(store (OpNode (load diraddrmode:$dst), CPURegs:$b), diraddrmode:$dst)]>;
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class LogicR<bits<6> op, string instr_asm, SDNode OpNode> :
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ByteFormat< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, mem:$c),
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!strconcat(instr_asm, " $c"),
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[(set CPURegs:$dst, (OpNode (load diraddrmode:$c), CPURegs:$b))]>;
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class LogicI<bits<6> op, string instr_asm, SDNode OpNode, Operand Od> :
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LiteralFormat< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, " $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, Od:$c ))]>;
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def XORWF : LogicM<0x1,"xorwf",xor>;
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def XORFW : LogicR<0x1,"xorfw",xor>;
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def XORLW : LogicI<0x1,"xorlw",xor, so_imm>;
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def ANDWF : LogicM<0x1,"andwf",and>;
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def ANDFW : LogicR<0x1,"andfw",and>;
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def ANDLW : LogicI<0x1,"andlw",and, so_imm>;
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def IORWF : LogicM<0x1,"iorwf",or>;
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def IORFW : LogicR<0x1,"iorfw",or>;
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def IORLW : LogicI<0x1,"iorlw",or, so_imm>;
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/* For comparison before branch */
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def SDT_PIC16Cmp : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>]>;
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def SDTIntBinOpPIC16 : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
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SDTCisSameAs<1,2>, SDTCisInt<1>]>;
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def PIC16Cmp : SDNode<"PIC16ISD::Cmp",SDTIntBinOpPIC16, [SDNPOutFlag]>;
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def PIC16XORCC : SDNode<"PIC16ISD::XORCC",SDTIntBinOpPIC16, [SDNPOutFlag]>;
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def PIC16SUBCC : SDNode<"PIC16ISD::SUBCC",SDTIntBinOpPIC16, [SDNPOutFlag]>;
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def XORFWCC : LogicR<0x1,"xorfw",PIC16XORCC>;
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def XORLWCC : LogicI<0x1,"xorlw",PIC16XORCC, so_imm>;
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def SUBFWCC : Arith1R<0x1,"subfw",PIC16SUBCC>;
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def SUBLWCC : ArithI<0x1,"sublw",PIC16SUBCC, so_imm>;
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/* For branch conditions */
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def SDT_PIC16Branch : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>,
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SDTCisVT<1,i8>, SDTCisVT<2,i8>]>;
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def PIC16Branch : SDNode<"PIC16ISD::Branch",SDT_PIC16Branch,
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[SDNPHasChain, SDNPInFlag]>;
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def PIC16BTFSS : SDNode<"PIC16ISD::BTFSS",SDT_PIC16Branch,
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[SDNPHasChain, SDNPInFlag]>;
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def PIC16BTFSC : SDNode<"PIC16ISD::BTFSC",SDT_PIC16Branch,
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[SDNPHasChain, SDNPInFlag]>;
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class InstrBitTestCC<bits<4> op, string instr_asm,SDNode OpNode>:
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BitFormat< op,
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(outs),
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(ins brtarget:$target ,so_imm:$i, STATUSRegs:$s ),
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!strconcat(instr_asm, " $s, $i, $target"),
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[(OpNode bb:$target, so_imm:$i, STATUSRegs:$s )]>;
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def BTFSS : InstrBitTestCC<0x1,"btfss",PIC16BTFSS>;
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def BTFSC : InstrBitTestCC<0x1,"btfsc",PIC16BTFSC>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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let Defs = [STKPTR], Uses = [STKPTR] in {
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def ADJCALLSTACKDOWN : Pseudo<255, (outs), (ins i8imm:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start imm:$amt)]>;
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def ADJCALLSTACKUP : Pseudo<254, (outs), (ins i8imm:$amt),
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"!ADJCALLSTACKUP $amt",
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[(callseq_end imm:$amt)]>;
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}
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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def : Pat<(ret), (RETURN)>;
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