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https://github.com/c64scene-ar/llvm-6502.git
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42f562a169
This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1.4 KiB
LLVM
46 lines
1.4 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 < %s | \
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; RUN: FileCheck %s -check-prefix=LE-PIC
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; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 < %s | \
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; RUN: FileCheck %s -check-prefix=LE-STATIC
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; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 < %s | \
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; RUN: FileCheck %s -check-prefix=BE-PIC
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; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=CHECK-LDC1-SDC1
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@g0 = common global double 0.000000e+00, align 8
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; LE-PIC: test_ldc1:
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; LE-PIC: lwc1 $f0, 0(${{[0-9]+}})
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; LE-PIC: lwc1 $f1, 4(${{[0-9]+}})
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; LE-STATIC: test_ldc1:
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; LE-STATIC: lwc1 $f0, %lo(g0)(${{[0-9]+}})
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; LE-STATIC: lwc1 $f1, %lo(g0+4)(${{[0-9]+}})
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; BE-PIC: test_ldc1:
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; BE-PIC: lwc1 $f1, 0(${{[0-9]+}})
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; BE-PIC: lwc1 $f0, 4(${{[0-9]+}})
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; CHECK-LDC1-SDC1: test_ldc1:
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; CHECK-LDC1-SDC1: ldc1 $f{{[0-9]+}}
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define double @test_ldc1() {
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entry:
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%0 = load double* @g0, align 8
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ret double %0
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}
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; LE-PIC: test_sdc1:
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; LE-PIC: swc1 $f12, 0(${{[0-9]+}})
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; LE-PIC: swc1 $f13, 4(${{[0-9]+}})
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; LE-STATIC: test_sdc1:
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; LE-STATIC: swc1 $f12, %lo(g0)(${{[0-9]+}})
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; LE-STATIC: swc1 $f13, %lo(g0+4)(${{[0-9]+}})
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; BE-PIC: test_sdc1:
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; BE-PIC: swc1 $f13, 0(${{[0-9]+}})
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; BE-PIC: swc1 $f12, 4(${{[0-9]+}})
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; CHECK-LDC1-SDC1: test_sdc1:
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; CHECK-LDC1-SDC1: sdc1 $f{{[0-9]+}}
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define void @test_sdc1(double %a) {
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entry:
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store double %a, double* @g0, align 8
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ret void
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}
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