Evan Cheng 948f343a2f * Added integer div / rem. ... * Fixed a load folding bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25136 91177308-0d34-0410-b5e6-96231b3b80d8		2006-01-06 23:19:29 +00:00
..
Alpha	make 0 codegen much better	2006-01-06 19:41:51 +00:00
CBackend	yet more C++ standards-compliance stuff.	2005-12-27 10:40:34 +00:00
IA64	silence a bogus gcc warning	2006-01-06 17:56:38 +00:00
PowerPC	linkonce symbols have an extra indirection, just like weak ones do. This fixes	2006-01-06 01:04:03 +00:00
Skeleton	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
Sparc	silence a bogus gcc warning	2006-01-06 17:56:38 +00:00
SparcV8	silence a bogus gcc warning	2006-01-06 17:56:38 +00:00
SparcV9	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
X86	* Added integer div / rem.	2006-01-06 23:19:29 +00:00
Makefile
MRegisterInfo.cpp
SubtargetFeature.cpp
Target.td	Added field noResults to Instruction.	2005-12-26 09:11:45 +00:00
TargetData.cpp
TargetFrameInfo.cpp
TargetInstrInfo.cpp
TargetMachine.cpp
TargetMachineRegistry.cpp
TargetSchedInfo.cpp
TargetSchedule.td
TargetSelectionDAG.td	Added fpimm node for ConstantFP.	2006-01-05 02:07:49 +00:00
TargetSubtarget.cpp