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47579cf390
This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
367 lines
16 KiB
TableGen
367 lines
16 KiB
TableGen
//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target-independent scheduling interfaces which should
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// be implemented by each target which is using TableGen based scheduling.
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//
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// The SchedMachineModel is defined by subtargets for three categories of data:
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// 1. Basic properties for coarse grained instruction cost model.
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// 2. Scheduler Read/Write resources for simple per-opcode cost model.
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// 3. Instruction itineraties for detailed reservation tables.
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//
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// (1) Basic properties are defined by the SchedMachineModel
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// class. Target hooks allow subtargets to associate opcodes with
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// those properties.
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//
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// (2) A per-operand machine model can be implemented in any
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// combination of the following ways:
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//
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// A. Associate per-operand SchedReadWrite types with Instructions by
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// modifying the Instruction definition to inherit from Sched. For
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// each subtarget, define WriteRes and ReadAdvance to associate
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// processor resources and latency with each SchedReadWrite type.
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//
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// B. In each instruction definition, name an ItineraryClass. For each
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// subtarget, define ItinRW entries to map ItineraryClass to
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// per-operand SchedReadWrite types. Unlike method A, these types may
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// be subtarget specific and can be directly associated with resources
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// by defining SchedWriteRes and SchedReadAdvance.
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//
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// C. In the subtarget, map SchedReadWrite types to specific
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// opcodes. This overrides any SchedReadWrite types or
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// ItineraryClasses defined by the Instruction. As in method B, the
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// subtarget can directly associate resources with SchedReadWrite
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// types by defining SchedWriteRes and SchedReadAdvance.
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//
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// D. In either the target or subtarget, define SchedWriteVariant or
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// SchedReadVariant to map one SchedReadWrite type onto another
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// sequence of SchedReadWrite types. This allows dynamic selection of
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// an instruction's machine model via custom C++ code. It also allows
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// a machine-independent SchedReadWrite type to map to a sequence of
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// machine-dependent types.
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//
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// (3) A per-pipeline-stage machine model can be implemented by providing
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// Itineraries in addition to mapping instructions to ItineraryClasses.
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//===----------------------------------------------------------------------===//
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// Include legacy support for instruction itineraries.
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include "llvm/Target/TargetItinerary.td"
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class Instruction; // Forward def
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// DAG operator that interprets the DAG args as Instruction defs.
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def instrs;
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// DAG operator that interprets each DAG arg as a regex pattern for
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// matching Instruction opcode names.
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// The regex must match the beginning of the opcode (as in Python re.match).
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// To avoid matching prefixes, append '$' to the pattern.
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def instregex;
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// Define the SchedMachineModel and provide basic properties for
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// coarse grained instruction cost model. Default values for the
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// properties are defined in MCSchedModel. A value of "-1" in the
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// target description's SchedMachineModel indicates that the property
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// is not overriden by the target.
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//
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// Target hooks allow subtargets to associate LoadLatency and
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// HighLatency with groups of opcodes.
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class SchedMachineModel {
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int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.
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int MinLatency = -1; // Determines which instrucions are allowed in a group.
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// (-1) inorder (0) ooo, (1): inorder +var latencies.
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int ILPWindow = -1; // Cycles of latency likely hidden by hardware buffers.
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int LoadLatency = -1; // Cycles for loads to access the cache.
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int HighLatency = -1; // Approximation of cycles for "high latency" ops.
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int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.
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// Per-cycle resources tables.
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ProcessorItineraries Itineraries = NoItineraries;
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bit NoModel = 0; // Special tag to indicate missing machine model.
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}
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def NoSchedModel : SchedMachineModel {
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let NoModel = 1;
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}
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// Define a kind of processor resource that may be common across
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// similar subtargets.
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class ProcResourceKind;
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// Define a number of interchangeable processor resources. NumUnits
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// determines the throughput of instructions that require the resource.
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//
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// An optional Super resource may be given to model these resources as
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// a subset of the more general super resources. Using one of these
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// resources implies using one of the super resoruces.
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//
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// ProcResourceUnits normally model a few buffered resources within an
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// out-of-order engine that the compiler attempts to conserve.
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// Buffered resources may be held for multiple clock cycles, but the
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// scheduler does not pin them to a particular clock cycle relative to
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// instruction dispatch. Setting Buffered=0 changes this to an
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// in-order resource. In this case, the scheduler counts down from the
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// cycle that the instruction issues in-order, forcing an interlock
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// with subsequent instructions that require the same resource until
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// the number of ResourceCyles specified in WriteRes expire.
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//
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// SchedModel ties these units to a processor for any stand-alone defs
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// of this class. Instances of subclass ProcResource will be automatically
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// attached to a processor, so SchedModel is not needed.
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class ProcResourceUnits<ProcResourceKind kind, int num> {
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ProcResourceKind Kind = kind;
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int NumUnits = num;
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ProcResourceKind Super = ?;
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bit Buffered = 1;
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SchedMachineModel SchedModel = ?;
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}
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// EponymousProcResourceKind helps implement ProcResourceUnits by
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// allowing a ProcResourceUnits definition to reference itself. It
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// should not be referenced anywhere else.
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def EponymousProcResourceKind : ProcResourceKind;
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// Subtargets typically define processor resource kind and number of
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// units in one place.
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class ProcResource<int num> : ProcResourceKind,
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ProcResourceUnits<EponymousProcResourceKind, num>;
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// A target architecture may define SchedReadWrite types and associate
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// them with instruction operands.
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class SchedReadWrite;
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// List the per-operand types that map to the machine model of an
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// instruction. One SchedWrite type must be listed for each explicit
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// def operand in order. Additional SchedWrite types may optionally be
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// listed for implicit def operands. SchedRead types may optionally
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// be listed for use operands in order. The order of defs relative to
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// uses is insignificant. This way, the same SchedReadWrite list may
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// be used for multiple forms of an operation. For example, a
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// two-address instruction could have two tied operands or single
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// operand that both reads and writes a reg. In both cases we have a
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// single SchedWrite and single SchedRead in any order.
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class Sched<list<SchedReadWrite> schedrw> {
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list<SchedReadWrite> SchedRW = schedrw;
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}
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// Define a scheduler resource associated with a def operand.
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class SchedWrite : SchedReadWrite;
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def NoWrite : SchedWrite;
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// Define a scheduler resource associated with a use operand.
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class SchedRead : SchedReadWrite;
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// Define a SchedWrite that is modeled as a sequence of other
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// SchedWrites with additive latency. This allows a single operand to
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// be mapped the resources composed from a set of previously defined
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// SchedWrites.
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//
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// If the final write in this sequence is a SchedWriteVariant marked
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// Variadic, then the list of prior writes are distributed across all
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// operands after resolving the predicate for the final write.
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//
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// SchedModel silences warnings but is ignored.
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class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
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list<SchedWrite> Writes = writes;
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int Repeat = rep;
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SchedMachineModel SchedModel = ?;
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}
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// Define values common to WriteRes and SchedWriteRes.
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//
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// SchedModel ties these resources to a processor.
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class ProcWriteResources<list<ProcResourceKind> resources> {
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list<ProcResourceKind> ProcResources = resources;
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list<int> ResourceCycles = [];
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int Latency = 1;
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int NumMicroOps = 1;
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bit BeginGroup = 0;
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bit EndGroup = 0;
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// Allow a processor to mark some scheduling classes as unsupported
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// for stronger verification.
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bit Unsupported = 0;
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SchedMachineModel SchedModel = ?;
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}
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// Define the resources and latency of a SchedWrite. This will be used
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// directly by targets that have no itinerary classes. In this case,
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// SchedWrite is defined by the target, while WriteResources is
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// defined by the subtarget, and maps the SchedWrite to processor
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// resources.
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//
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// If a target already has itinerary classes, SchedWriteResources can
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// be used instead to define subtarget specific SchedWrites and map
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// them to processor resources in one place. Then ItinRW can map
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// itinerary classes to the subtarget's SchedWrites.
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//
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// ProcResources indicates the set of resources consumed by the write.
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// Optionally, ResourceCycles indicates the number of cycles the
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// resource is consumed. Each ResourceCycles item is paired with the
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// ProcResource item at the same position in its list. Since
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// ResourceCycles are rarely specialized, the list may be
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// incomplete. By default, resources are consumed for a single cycle,
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// regardless of latency, which models a fully pipelined processing
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// unit. A value of 0 for ResourceCycles means that the resource must
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// be available but is not consumed, which is only relevant for
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// unbuffered resources.
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//
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// By default, each SchedWrite takes one micro-op, which is counted
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// against the processor's IssueWidth limit. If an instruction can
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// write multiple registers with a single micro-op, the subtarget
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// should define one of the writes to be zero micro-ops. If a
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// subtarget requires multiple micro-ops to write a single result, it
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// should either override the write's NumMicroOps to be greater than 1
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// or require additional writes. Extra writes can be required either
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// by defining a WriteSequence, or simply listing extra writes in the
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// instruction's list of writers beyond the number of "def"
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// operands. The scheduler assumes that all micro-ops must be
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// dispatched in the same cycle. These micro-ops may be required to
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// begin or end the current dispatch group.
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class WriteRes<SchedWrite write, list<ProcResourceKind> resources>
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: ProcWriteResources<resources> {
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SchedWrite WriteType = write;
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}
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// Directly name a set of WriteResources defining a new SchedWrite
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// type at the same time. This class is unaware of its SchedModel so
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// must be referenced by InstRW or ItinRW.
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class SchedWriteRes<list<ProcResourceKind> resources> : SchedWrite,
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ProcWriteResources<resources>;
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// Define values common to ReadAdvance and SchedReadAdvance.
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//
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// SchedModel ties these resources to a processor.
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class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> {
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int Cycles = cycles;
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list<SchedWrite> ValidWrites = writes;
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// Allow a processor to mark some scheduling classes as unsupported
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// for stronger verification.
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bit Unsupported = 0;
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SchedMachineModel SchedModel = ?;
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}
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// A processor may define a ReadAdvance associated with a SchedRead
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// to reduce latency of a prior write by N cycles. A negative advance
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// effectively increases latency, which may be used for cross-domain
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// stalls.
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//
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// A ReadAdvance may be associated with a list of SchedWrites
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// to implement pipeline bypass. The Writes list may be empty to
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// indicate operands that are always read this number of Cycles later
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// than a normal register read, allowing the read's parent instruction
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// to issue earlier relative to the writer.
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class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
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: ProcReadAdvance<cycles, writes> {
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SchedRead ReadType = read;
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}
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// Directly associate a new SchedRead type with a delay and optional
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// pipeline bypess. For use with InstRW or ItinRW.
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class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRead,
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ProcReadAdvance<cycles, writes>;
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// Define SchedRead defaults. Reads seldom need special treatment.
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def ReadDefault : SchedRead;
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def NoReadAdvance : SchedReadAdvance<0>;
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// Define shared code that will be in the same scope as all
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// SchedPredicates. Available variables are:
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// (const MachineInstr *MI, const TargetSchedModel *SchedModel)
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class PredicateProlog<code c> {
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code Code = c;
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}
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// Define a predicate to determine which SchedVariant applies to a
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// particular MachineInstr. The code snippet is used as an
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// if-statement's expression. Available variables are MI, SchedModel,
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// and anything defined in a PredicateProlog.
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//
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// SchedModel silences warnings but is ignored.
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class SchedPredicate<code pred> {
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SchedMachineModel SchedModel = ?;
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code Predicate = pred;
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}
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def NoSchedPred : SchedPredicate<[{true}]>;
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// Associate a predicate with a list of SchedReadWrites. By default,
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// the selected SchedReadWrites are still associated with a single
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// operand and assumed to execute sequentially with additive
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// latency. However, if the parent SchedWriteVariant or
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// SchedReadVariant is marked "Variadic", then each Selected
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// SchedReadWrite is mapped in place to the instruction's variadic
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// operands. In this case, latency is not additive. If the current Variant
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// is already part of a Sequence, then that entire chain leading up to
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// the Variant is distributed over the variadic operands.
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class SchedVar<SchedPredicate pred, list<SchedReadWrite> selected> {
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SchedPredicate Predicate = pred;
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list<SchedReadWrite> Selected = selected;
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}
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// SchedModel silences warnings but is ignored.
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class SchedVariant<list<SchedVar> variants> {
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list<SchedVar> Variants = variants;
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bit Variadic = 0;
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SchedMachineModel SchedModel = ?;
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}
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// A SchedWriteVariant is a single SchedWrite type that maps to a list
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// of SchedWrite types under the conditions defined by its predicates.
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//
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// A Variadic write is expanded to cover multiple "def" operands. The
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// SchedVariant's Expansion list is then interpreted as one write
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// per-operand instead of the usual sequential writes feeding a single
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// operand.
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class SchedWriteVariant<list<SchedVar> variants> : SchedWrite,
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SchedVariant<variants> {
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}
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// A SchedReadVariant is a single SchedRead type that maps to a list
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// of SchedRead types under the conditions defined by its predicates.
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//
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// A Variadic write is expanded to cover multiple "readsReg" operands as
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// explained above.
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class SchedReadVariant<list<SchedVar> variants> : SchedRead,
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SchedVariant<variants> {
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}
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// Map a set of opcodes to a list of SchedReadWrite types. This allows
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// the subtarget to easily override specific operations.
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//
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// SchedModel ties this opcode mapping to a processor.
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class InstRW<list<SchedReadWrite> rw, dag instrlist> {
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list<SchedReadWrite> OperandReadWrites = rw;
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dag Instrs = instrlist;
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SchedMachineModel SchedModel = ?;
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}
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// Map a set of itinerary classes to SchedReadWrite resources. This is
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// used to bootstrap a target (e.g. ARM) when itineraries already
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// exist and changing InstrInfo is undesirable.
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//
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// SchedModel ties this ItineraryClass mapping to a processor.
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class ItinRW<list<SchedReadWrite> rw, list<InstrItinClass> iic> {
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list<InstrItinClass> MatchedItinClasses = iic;
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list<SchedReadWrite> OperandReadWrites = rw;
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SchedMachineModel SchedModel = ?;
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}
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// Alias a target-defined SchedReadWrite to a processor specific
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// SchedReadWrite. This allows a subtarget to easily map a
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// SchedReadWrite type onto a WriteSequence, SchedWriteVariant, or
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// SchedReadVariant.
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//
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// SchedModel will usually be provided by surrounding let statement
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// and ties this SchedAlias mapping to a processor.
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class SchedAlias<SchedReadWrite match, SchedReadWrite alias> {
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SchedReadWrite MatchRW = match;
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SchedReadWrite AliasRW = alias;
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SchedMachineModel SchedModel = ?;
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}
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