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Reg-units are named after their root registers, and most units have a single root, so they simply print as 'AL', 'XMM0', etc. The rare dual root reg-units print as FPSCR~FPSCR_NZCV, FP0~ST7, ... The printing piggybacks on the existing register name tables, so no extra const data space is required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157754 91177308-0d34-0410-b5e6-96231b3b80d8
247 lines
8.7 KiB
C++
247 lines
8.7 KiB
C++
//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetRegisterInfo interface.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
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regclass_iterator RCB, regclass_iterator RCE,
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const char *const *subregindexnames)
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: InfoDesc(ID), SubRegIndexNames(subregindexnames),
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RegClassBegin(RCB), RegClassEnd(RCE) {
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}
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TargetRegisterInfo::~TargetRegisterInfo() {}
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void PrintReg::print(raw_ostream &OS) const {
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if (!Reg)
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OS << "%noreg";
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else if (TargetRegisterInfo::isStackSlot(Reg))
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OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
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else if (TargetRegisterInfo::isVirtualRegister(Reg))
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OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
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else if (TRI && Reg < TRI->getNumRegs())
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OS << '%' << TRI->getName(Reg);
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else
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OS << "%physreg" << Reg;
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if (SubIdx) {
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if (TRI)
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OS << ':' << TRI->getSubRegIndexName(SubIdx);
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else
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OS << ":sub(" << SubIdx << ')';
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}
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}
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void PrintRegUnit::print(raw_ostream &OS) const {
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// Generic printout when TRI is missing.
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if (!TRI) {
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OS << "Unit~" << Unit;
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return;
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}
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// Check for invalid register units.
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if (Unit >= TRI->getNumRegUnits()) {
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OS << "BadUnit~" << Unit;
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return;
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}
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// Normal units have at least one root.
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MCRegUnitRootIterator Roots(Unit, TRI);
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assert(Roots.isValid() && "Unit has no roots.");
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OS << TRI->getName(*Roots);
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for (++Roots; Roots.isValid(); ++Roots)
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OS << '~' << TRI->getName(*Roots);
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}
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/// getAllocatableClass - Return the maximal subclass of the given register
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/// class that is alloctable, or NULL.
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const TargetRegisterClass *
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TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
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if (!RC || RC->isAllocatable())
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return RC;
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const unsigned *SubClass = RC->getSubClassMask();
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for (unsigned Base = 0, BaseE = getNumRegClasses();
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Base < BaseE; Base += 32) {
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unsigned Idx = Base;
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for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
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unsigned Offset = CountTrailingZeros_32(Mask);
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const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
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if (SubRC->isAllocatable())
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return SubRC;
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Mask >>= Offset;
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Idx += Offset + 1;
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}
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}
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return NULL;
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}
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/// getMinimalPhysRegClass - Returns the Register Class of a physical
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/// register of the given type, picking the most sub register class of
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/// the right type that contains this physreg.
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const TargetRegisterClass *
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TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
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assert(isPhysicalRegister(reg) && "reg must be a physical register");
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// Pick the most sub register class of the right type that contains
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// this physreg.
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const TargetRegisterClass* BestRC = 0;
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for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
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const TargetRegisterClass* RC = *I;
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if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
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(!BestRC || BestRC->hasSubClass(RC)))
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BestRC = RC;
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}
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assert(BestRC && "Couldn't find the register class");
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return BestRC;
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}
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/// getAllocatableSetForRC - Toggle the bits that represent allocatable
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/// registers for the specific register class.
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static void getAllocatableSetForRC(const MachineFunction &MF,
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const TargetRegisterClass *RC, BitVector &R){
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assert(RC->isAllocatable() && "invalid for nonallocatable sets");
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ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
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for (unsigned i = 0; i != Order.size(); ++i)
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R.set(Order[i]);
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}
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BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
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const TargetRegisterClass *RC) const {
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BitVector Allocatable(getNumRegs());
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if (RC) {
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// A register class with no allocatable subclass returns an empty set.
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const TargetRegisterClass *SubClass = getAllocatableClass(RC);
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if (SubClass)
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getAllocatableSetForRC(MF, SubClass, Allocatable);
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} else {
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for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
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E = regclass_end(); I != E; ++I)
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if ((*I)->isAllocatable())
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getAllocatableSetForRC(MF, *I, Allocatable);
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}
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// Mask out the reserved registers
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BitVector Reserved = getReservedRegs(MF);
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Allocatable &= Reserved.flip();
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return Allocatable;
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}
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static inline
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const TargetRegisterClass *firstCommonClass(const uint32_t *A,
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const uint32_t *B,
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const TargetRegisterInfo *TRI) {
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for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
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if (unsigned Common = *A++ & *B++)
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return TRI->getRegClass(I + CountTrailingZeros_32(Common));
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return 0;
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}
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const TargetRegisterClass *
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TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B) const {
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// First take care of the trivial cases.
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if (A == B)
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return A;
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if (!A || !B)
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return 0;
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// Register classes are ordered topologically, so the largest common
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// sub-class it the common sub-class with the smallest ID.
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return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
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}
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const TargetRegisterClass *
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TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B,
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unsigned Idx) const {
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assert(A && B && "Missing register class");
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assert(Idx && "Bad sub-register index");
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// Find Idx in the list of super-register indices.
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for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
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if (RCI.getSubReg() == Idx)
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// The bit mask contains all register classes that are projected into B
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// by Idx. Find a class that is also a sub-class of A.
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return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
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return 0;
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}
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const TargetRegisterClass *TargetRegisterInfo::
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getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
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const TargetRegisterClass *RCB, unsigned SubB,
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unsigned &PreA, unsigned &PreB) const {
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assert(RCA && SubA && RCB && SubB && "Invalid arguments");
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// Search all pairs of sub-register indices that project into RCA and RCB
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// respectively. This is quadratic, but usually the sets are very small. On
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// most targets like X86, there will only be a single sub-register index
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// (e.g., sub_16bit projecting into GR16).
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//
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// The worst case is a register class like DPR on ARM.
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// We have indices dsub_0..dsub_7 projecting into that class.
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//
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// It is very common that one register class is a sub-register of the other.
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// Arrange for RCA to be the larger register so the answer will be found in
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// the first iteration. This makes the search linear for the most common
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// case.
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const TargetRegisterClass *BestRC = 0;
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unsigned *BestPreA = &PreA;
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unsigned *BestPreB = &PreB;
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if (RCA->getSize() < RCB->getSize()) {
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std::swap(RCA, RCB);
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std::swap(SubA, SubB);
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std::swap(BestPreA, BestPreB);
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}
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// Also terminate the search one we have found a register class as small as
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// RCA.
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unsigned MinSize = RCA->getSize();
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for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
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unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
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for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
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// Check if a common super-register class exists for this index pair.
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const TargetRegisterClass *RC =
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firstCommonClass(IA.getMask(), IB.getMask(), this);
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if (!RC || RC->getSize() < MinSize)
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continue;
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// The indexes must compose identically: PreA+SubA == PreB+SubB.
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unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
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if (FinalA != FinalB)
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continue;
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// Is RC a better candidate than BestRC?
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if (BestRC && RC->getSize() >= BestRC->getSize())
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continue;
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// Yes, RC is the smallest super-register seen so far.
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BestRC = RC;
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*BestPreA = IA.getSubReg();
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*BestPreB = IB.getSubReg();
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// Bail early if we reached MinSize. We won't find a better candidate.
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if (BestRC->getSize() == MinSize)
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return BestRC;
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}
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}
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return BestRC;
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}
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