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function can support dynamic stack realignment. That's a much easier question to answer at instruction selection stage than whether the function actually will have dynamic alignment prologue. This allows the removal of the stack alignment heuristic pass, and improves code quality for cases where the heuristic would result in dynamic alignment code being generated when it was not strictly necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93885 91177308-0d34-0410-b5e6-96231b3b80d8
164 lines
5.6 KiB
C++
164 lines
5.6 KiB
C++
//===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the base ARM implementation of TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMBASEREGISTERINFO_H
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#define ARMBASEREGISTERINFO_H
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#include "ARM.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "ARMGenRegisterInfo.h.inc"
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namespace llvm {
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class ARMSubtarget;
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class ARMBaseInstrInfo;
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class Type;
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/// Register allocation hints.
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namespace ARMRI {
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enum {
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RegPairOdd = 1,
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RegPairEven = 2
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};
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}
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/// isARMLowRegister - Returns true if the register is low register r0-r7.
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///
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static inline bool isARMLowRegister(unsigned Reg) {
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using namespace ARM;
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switch (Reg) {
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case R0: case R1: case R2: case R3:
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case R4: case R5: case R6: case R7:
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return true;
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default:
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return false;
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}
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}
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struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
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protected:
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const ARMBaseInstrInfo &TII;
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const ARMSubtarget &STI;
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/// FramePtr - ARM physical register used as frame ptr.
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unsigned FramePtr;
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// Can be only subclassed.
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explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
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const ARMSubtarget &STI);
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// Return the opcode that implements 'Op', or 0 if no opcode
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unsigned getOpcode(int Op) const;
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public:
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// ARM::LR, return the number that it corresponds to (e.g. 14). It
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/// also returns true in isSPVFP if the register is a single precision
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/// VFP register.
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static unsigned getRegisterNumbering(unsigned RegEnum, bool *isSPVFP = 0);
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/// Code Generation virtual methods...
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const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const TargetRegisterClass* const*
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getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
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BitVector getReservedRegs(const MachineFunction &MF) const;
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/// getMatchingSuperRegClass - Return a subclass of the specified register
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/// class A so that each register in it has a sub-register of the
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/// specified sub-register index which is in the specified register class B.
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virtual const TargetRegisterClass *
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getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B, unsigned Idx) const;
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const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
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std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
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getAllocationOrder(const TargetRegisterClass *RC,
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unsigned HintType, unsigned HintReg,
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const MachineFunction &MF) const;
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unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
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const MachineFunction &MF) const;
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void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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bool canRealignStack(const MachineFunction &MF) const;
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bool needsStackRealignment(const MachineFunction &MF) const;
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bool cannotEliminateFrame(const MachineFunction &MF) const;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS = NULL) const;
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// Debug information queries.
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unsigned getRARegister() const;
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unsigned getFrameRegister(const MachineFunction &MF) const;
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int getFrameIndexReference(MachineFunction &MF, int FI,
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unsigned &FrameReg) const;
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int getFrameIndexOffset(MachineFunction &MF, int FI) const;
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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bool isLowRegister(unsigned Reg) const;
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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virtual void emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned SubIdx,
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int Val,
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ARMCC::CondCodes Pred = ARMCC::AL,
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unsigned PredReg = 0) const;
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/// Code Generation virtual methods...
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virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
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virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
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virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
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virtual bool hasReservedCallFrame(MachineFunction &MF) const;
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virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, int *Value = NULL,
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RegScavenger *RS = NULL) const;
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virtual void emitPrologue(MachineFunction &MF) const;
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virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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private:
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unsigned estimateRSStackSizeLimit(MachineFunction &MF) const;
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unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
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unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
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};
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} // end namespace llvm
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#endif
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