llvm-6502/test/CodeGen
2014-08-05 14:48:12 +00:00
..
AArch64 AArch64: Add support for instruction prefetch intrinsic 2014-08-05 12:46:47 +00:00
ARM [ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly 2014-08-02 05:40:40 +00:00
CPP
Generic
Hexagon
Inputs
Mips llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll: Add explicit -mtriple=(mips|mipsel)-linux on 4 lines. 2014-08-01 22:15:38 +00:00
MSP430
NVPTX
PowerPC [PPC64LE] Fix wrong IR for vec_sld and vec_vsldoi 2014-08-04 23:21:01 +00:00
R600 R600/SI: Update MUBUF assembly string to match AMD proprietary compiler 2014-08-05 14:48:12 +00:00
SPARC
SystemZ
Thumb [ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly 2014-08-02 05:40:40 +00:00
Thumb2 [ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly 2014-08-02 05:40:40 +00:00
X86 [x86] Fix a crash and wrong-code bug in the new vector lowering all 2014-08-05 08:19:21 +00:00
XCore