mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4809 91177308-0d34-0410-b5e6-96231b3b80d8
587 lines
21 KiB
C++
587 lines
21 KiB
C++
//===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
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//
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// This file defines a simple peephole instruction selector for the x86 platform
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86InstrBuilder.h"
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#include "llvm/Function.h"
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#include "llvm/iTerminators.h"
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#include "llvm/iOperators.h"
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#include "llvm/iOther.h"
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#include "llvm/iPHINode.h"
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#include "llvm/iMemory.h"
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#include "llvm/Type.h"
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#include "llvm/Constants.h"
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#include "llvm/Pass.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/InstVisitor.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include <map>
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using namespace MOTy; // Get Use, Def, UseAndDef
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namespace {
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struct ISel : public FunctionPass, InstVisitor<ISel> {
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TargetMachine &TM;
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MachineFunction *F; // The function we are compiling into
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MachineBasicBlock *BB; // The current MBB we are compiling
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unsigned CurReg;
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std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
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ISel(TargetMachine &tm)
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: TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
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/// runOnFunction - Top level implementation of instruction selection for
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/// the entire function.
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///
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bool runOnFunction(Function &Fn) {
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F = &MachineFunction::construct(&Fn, TM);
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visit(Fn);
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RegMap.clear();
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CurReg = MRegisterInfo::FirstVirtualRegister;
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F = 0;
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return false; // We never modify the LLVM itself.
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}
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/// visitBasicBlock - This method is called when we are visiting a new basic
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/// block. This simply creates a new MachineBasicBlock to emit code into
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/// and adds it to the current MachineFunction. Subsequent visit* for
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/// instructions will be invoked for all instructions in the basic block.
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///
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void visitBasicBlock(BasicBlock &LLVM_BB) {
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BB = new MachineBasicBlock(&LLVM_BB);
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// FIXME: Use the auto-insert form when it's available
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F->getBasicBlockList().push_back(BB);
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}
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// Visitation methods for various instructions. These methods simply emit
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// fixed X86 code for each instruction.
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//
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void visitReturnInst(ReturnInst &RI);
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void visitBranchInst(BranchInst &BI);
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// Arithmetic operators
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void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
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void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
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void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
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void visitMul(BinaryOperator &B);
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void visitDiv(BinaryOperator &B) { visitDivRem(B); }
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void visitRem(BinaryOperator &B) { visitDivRem(B); }
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void visitDivRem(BinaryOperator &B);
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// Bitwise operators
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void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
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void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
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void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
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// Binary comparison operators
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void visitSetCCInst(SetCondInst &I, unsigned OpNum);
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void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
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void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
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void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
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void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
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void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
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void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
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// Memory Instructions
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void visitLoadInst(LoadInst &I);
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void visitStoreInst(StoreInst &I);
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// Other operators
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void visitShiftInst(ShiftInst &I);
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void visitPHINode(PHINode &I);
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void visitInstruction(Instruction &I) {
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std::cerr << "Cannot instruction select: " << I;
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abort();
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}
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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void copyConstantToRegister(Constant *C, unsigned Reg);
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/// getReg - This method turns an LLVM value into a register number. This
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/// is guaranteed to produce the same register number for a particular value
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/// every time it is queried.
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///
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unsigned getReg(Value &V) { return getReg(&V); } // Allow references
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unsigned getReg(Value *V) {
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unsigned &Reg = RegMap[V];
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if (Reg == 0) {
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Reg = CurReg++;
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RegMap[V] = Reg;
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// Add the mapping of regnumber => reg class to MachineFunction
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F->addRegMap(Reg,
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TM.getRegisterInfo()->getRegClassForType(V->getType()));
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}
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// If this operand is a constant, emit the code to copy the constant into
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// the register here...
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//
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if (Constant *C = dyn_cast<Constant>(V))
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copyConstantToRegister(C, Reg);
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return Reg;
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}
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};
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}
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/// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
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/// Representation.
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///
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enum TypeClass {
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cByte, cShort, cInt, cLong, cFloat, cDouble
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};
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/// getClass - Turn a primitive type into a "class" number which is based on the
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/// size of the type, and whether or not it is floating point.
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///
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static inline TypeClass getClass(const Type *Ty) {
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switch (Ty->getPrimitiveID()) {
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case Type::SByteTyID:
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case Type::UByteTyID: return cByte; // Byte operands are class #0
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case Type::ShortTyID:
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case Type::UShortTyID: return cShort; // Short operands are class #1
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return cInt; // Int's and pointers are class #2
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case Type::LongTyID:
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case Type::ULongTyID: return cLong; // Longs are class #3
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case Type::FloatTyID: return cFloat; // Float is class #4
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case Type::DoubleTyID: return cDouble; // Doubles are class #5
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default:
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assert(0 && "Invalid type to getClass!");
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return cByte; // not reached
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}
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}
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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void ISel::copyConstantToRegister(Constant *C, unsigned R) {
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assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
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if (C->getType()->isIntegral()) {
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unsigned Class = getClass(C->getType());
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assert(Class != 3 && "Type not handled yet!");
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static const unsigned IntegralOpcodeTab[] = {
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X86::MOVir8, X86::MOVir16, X86::MOVir32
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};
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if (C->getType()->isSigned()) {
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ConstantSInt *CSI = cast<ConstantSInt>(C);
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BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
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} else {
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ConstantUInt *CUI = cast<ConstantUInt>(C);
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BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
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}
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} else {
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assert(0 && "Type not handled yet!");
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}
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}
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/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
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/// register, then move it to wherever the result should be.
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/// We handle FP setcc instructions by pushing them, doing a
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/// compare-and-pop-twice, and then copying the concodes to the main
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/// processor's concodes (I didn't make this up, it's in the Intel manual)
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///
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void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
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// The arguments are already supposed to be of the same type.
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const Type *CompTy = I.getOperand(0)->getType();
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unsigned reg1 = getReg(I.getOperand(0));
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unsigned reg2 = getReg(I.getOperand(1));
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unsigned Class = getClass(CompTy);
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switch (Class) {
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// Emit: cmp <var1>, <var2> (do the comparison). We can
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// compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
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// 32-bit.
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case cByte:
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BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
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break;
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case cShort:
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BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
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break;
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case cInt:
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BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
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break;
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// Push the variables on the stack with fldl opcodes.
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// FIXME: assuming var1, var2 are in memory, if not, spill to
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// stack first
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case cFloat: // Floats
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
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break;
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case cDouble: // Doubles
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
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break;
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case cLong:
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default:
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visitInstruction(I);
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}
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if (CompTy->isFloatingPoint()) {
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// (Non-trapping) compare and pop twice.
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BuildMI (BB, X86::FUCOMPP, 0);
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// Move fp status word (concodes) to ax.
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BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
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// Load real concodes from ax.
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BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
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}
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// Emit setOp instruction (extract concode; clobbers ax),
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// using the following mapping:
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// LLVM -> X86 signed X86 unsigned
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// ----- ----- -----
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// seteq -> sete sete
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// setne -> setne setne
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// setlt -> setl setb
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// setgt -> setg seta
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// setle -> setle setbe
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// setge -> setge setae
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static const unsigned OpcodeTab[2][6] = {
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{X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAr, X86::SETBEr, X86::SETAEr},
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{X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGr, X86::SETLEr, X86::SETGEr},
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};
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BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL);
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// Put it in the result using a move.
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BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL);
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}
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/// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
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/// we have the following possibilities:
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///
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/// ret void: No return value, simply emit a 'ret' instruction
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/// ret sbyte, ubyte : Extend value into EAX and return
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/// ret short, ushort: Extend value into EAX and return
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/// ret int, uint : Move value into EAX and return
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/// ret pointer : Move value into EAX and return
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/// ret long, ulong : Move value into EAX/EDX and return
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/// ret float/double : Top of FP stack
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///
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void ISel::visitReturnInst (ReturnInst &I) {
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if (I.getNumOperands() == 0) {
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// Emit a 'ret' instruction
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BuildMI(BB, X86::RET, 0);
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return;
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}
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unsigned val = getReg(I.getOperand(0));
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unsigned Class = getClass(I.getOperand(0)->getType());
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bool isUnsigned = I.getOperand(0)->getType()->isUnsigned();
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switch (Class) {
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case cByte:
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// ret sbyte, ubyte: Extend value into EAX and return
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if (isUnsigned)
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BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val);
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else
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BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val);
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break;
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case cShort:
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// ret short, ushort: Extend value into EAX and return
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if (isUnsigned)
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BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val);
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else
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BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val);
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break;
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case cInt:
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// ret int, uint, ptr: Move value into EAX and return
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// MOV EAX, <val>
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BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(val);
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break;
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// ret float/double: top of FP stack
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// FLD <val>
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case cFloat: // Floats
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BuildMI(BB, X86::FLDr4, 1).addReg(val);
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break;
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case cDouble: // Doubles
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BuildMI(BB, X86::FLDr8, 1).addReg(val);
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break;
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case cLong:
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// ret long: use EAX(least significant 32 bits)/EDX (most
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// significant 32)...uh, I think so Brain, but how do i call
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// up the two parts of the value from inside this mouse
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// cage? *zort*
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default:
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visitInstruction(I);
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}
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// Emit a 'ret' instruction
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BuildMI(BB, X86::RET, 0);
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}
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/// visitBranchInst - Handle conditional and unconditional branches here. Note
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/// that since code layout is frozen at this point, that if we are trying to
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/// jump to a block that is the immediate successor of the current block, we can
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/// just make a fall-through. (but we don't currently).
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///
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void
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ISel::visitBranchInst (BranchInst & BI)
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{
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if (BI.isConditional ())
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{
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BasicBlock *ifTrue = BI.getSuccessor (0);
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BasicBlock *ifFalse = BI.getSuccessor (1); // this is really unobvious
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// simplest thing I can think of: compare condition with zero,
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// followed by jump-if-equal to ifFalse, and jump-if-nonequal to
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// ifTrue
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unsigned int condReg = getReg (BI.getCondition ());
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BuildMI (BB, X86::CMPri8, 2).addReg (condReg).addZImm (0);
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BuildMI (BB, X86::JNE, 1).addPCDisp (BI.getSuccessor (0));
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BuildMI (BB, X86::JE, 1).addPCDisp (BI.getSuccessor (1));
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}
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else // unconditional branch
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{
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BuildMI (BB, X86::JMP, 1).addPCDisp (BI.getSuccessor (0));
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}
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}
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/// visitSimpleBinary - Implement simple binary operators for integral types...
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/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
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/// 4 for Xor.
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///
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void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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if (B.getType() == Type::BoolTy) // FIXME: Handle bools for logicals
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visitInstruction(B);
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unsigned Class = getClass(B.getType());
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if (Class > 2) // FIXME: Handle longs
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visitInstruction(B);
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static const unsigned OpcodeTab[][4] = {
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// Arithmetic operators
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{ X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, 0 }, // ADD
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{ X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, 0 }, // SUB
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// Bitwise operators
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{ X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
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{ X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
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{ X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
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};
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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unsigned Op0r = getReg(B.getOperand(0));
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unsigned Op1r = getReg(B.getOperand(1));
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BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
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}
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/// visitMul - Multiplies are not simple binary operators because they must deal
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/// with the EAX register explicitly.
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///
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void ISel::visitMul(BinaryOperator &I) {
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unsigned Class = getClass(I.getType());
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if (Class > 2) // FIXME: Handle longs
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visitInstruction(I);
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static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
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static const unsigned Clobbers[] ={ X86::AH , X86::DX , X86::EDX };
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static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
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static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
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unsigned Reg = Regs[Class];
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unsigned Clobber = Clobbers[Class];
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unsigned Op0Reg = getReg(I.getOperand(0));
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unsigned Op1Reg = getReg(I.getOperand(1));
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// Put the first operand into one of the A registers...
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BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
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// Emit the appropriate multiply instruction...
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BuildMI(BB, MulOpcode[Class], 3)
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.addReg(Reg, UseAndDef).addReg(Op1Reg).addClobber(Clobber);
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// Put the result into the destination register...
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BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg);
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}
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/// visitDivRem - Handle division and remainder instructions... these
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/// instruction both require the same instructions to be generated, they just
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/// select the result from a different register. Note that both of these
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/// instructions work differently for signed and unsigned operands.
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///
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void ISel::visitDivRem(BinaryOperator &I) {
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unsigned Class = getClass(I.getType());
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if (Class > 2) // FIXME: Handle longs
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visitInstruction(I);
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static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
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static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
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static const unsigned ExtOpcode[]={ X86::CBW , X86::CWD , X86::CDQ };
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static const unsigned ClrOpcode[]={ X86::XORrr8, X86::XORrr16, X86::XORrr32 };
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static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
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static const unsigned DivOpcode[][4] = {
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{ X86::DIVrr8 , X86::DIVrr16 , X86::DIVrr32 , 0 }, // Unsigned division
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{ X86::IDIVrr8, X86::IDIVrr16, X86::IDIVrr32, 0 }, // Signed division
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};
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bool isSigned = I.getType()->isSigned();
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unsigned Reg = Regs[Class];
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unsigned ExtReg = ExtRegs[Class];
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unsigned Op0Reg = getReg(I.getOperand(0));
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unsigned Op1Reg = getReg(I.getOperand(1));
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// Put the first operand into one of the A registers...
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BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
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if (isSigned) {
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// Emit a sign extension instruction...
|
|
BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg);
|
|
} else {
|
|
// If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
|
|
BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
|
|
}
|
|
|
|
// Emit the appropriate divide or remainder instruction...
|
|
BuildMI(BB, DivOpcode[isSigned][Class], 2)
|
|
.addReg(Reg, UseAndDef).addReg(ExtReg, UseAndDef).addReg(Op1Reg);
|
|
|
|
// Figure out which register we want to pick the result out of...
|
|
unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
|
|
|
|
// Put the result into the destination register...
|
|
BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(DestReg);
|
|
}
|
|
|
|
|
|
/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
|
|
/// for constant immediate shift values, and for constant immediate
|
|
/// shift values equal to 1. Even the general case is sort of special,
|
|
/// because the shift amount has to be in CL, not just any old register.
|
|
///
|
|
void ISel::visitShiftInst (ShiftInst &I) {
|
|
unsigned Op0r = getReg (I.getOperand(0));
|
|
unsigned DestReg = getReg(I);
|
|
bool isLeftShift = I.getOpcode() == Instruction::Shl;
|
|
bool isOperandSigned = I.getType()->isUnsigned();
|
|
unsigned OperandClass = getClass(I.getType());
|
|
|
|
if (OperandClass > 2)
|
|
visitInstruction(I); // Can't handle longs yet!
|
|
|
|
if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
|
|
{
|
|
// The shift amount is constant, guaranteed to be a ubyte. Get its value.
|
|
assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
|
|
unsigned char shAmt = CUI->getValue();
|
|
|
|
static const unsigned ConstantOperand[][4] = {
|
|
{ X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
|
|
{ X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
|
|
{ X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
|
|
{ X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
|
|
};
|
|
|
|
const unsigned *OpTab = // Figure out the operand table to use
|
|
ConstantOperand[isLeftShift*2+isOperandSigned];
|
|
|
|
// Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
|
|
BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
|
|
}
|
|
else
|
|
{
|
|
// The shift amount is non-constant.
|
|
//
|
|
// In fact, you can only shift with a variable shift amount if
|
|
// that amount is already in the CL register, so we have to put it
|
|
// there first.
|
|
//
|
|
|
|
// Emit: move cl, shiftAmount (put the shift amount in CL.)
|
|
BuildMI(BB, X86::MOVrr8, 1, X86::CL).addReg(getReg(I.getOperand(1)));
|
|
|
|
// This is a shift right (SHR).
|
|
static const unsigned NonConstantOperand[][4] = {
|
|
{ X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
|
|
{ X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
|
|
{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
|
|
{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
|
|
};
|
|
|
|
const unsigned *OpTab = // Figure out the operand table to use
|
|
NonConstantOperand[isLeftShift*2+isOperandSigned];
|
|
|
|
BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
|
|
}
|
|
}
|
|
|
|
|
|
/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
|
|
/// instruction.
|
|
///
|
|
void ISel::visitLoadInst(LoadInst &I) {
|
|
unsigned Class = getClass(I.getType());
|
|
if (Class > 2) // FIXME: Handle longs and others...
|
|
visitInstruction(I);
|
|
|
|
static const unsigned Opcode[] = { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32 };
|
|
|
|
unsigned AddressReg = getReg(I.getOperand(0));
|
|
addDirectMem(BuildMI(BB, Opcode[Class], 4, getReg(I)), AddressReg);
|
|
}
|
|
|
|
|
|
/// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
|
|
/// instruction.
|
|
///
|
|
void ISel::visitStoreInst(StoreInst &I) {
|
|
unsigned Class = getClass(I.getOperand(0)->getType());
|
|
if (Class > 2) // FIXME: Handle longs and others...
|
|
visitInstruction(I);
|
|
|
|
static const unsigned Opcode[] = { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32 };
|
|
|
|
unsigned ValReg = getReg(I.getOperand(0));
|
|
unsigned AddressReg = getReg(I.getOperand(1));
|
|
addDirectMem(BuildMI(BB, Opcode[Class], 1+4), AddressReg).addReg(ValReg);
|
|
}
|
|
|
|
|
|
/// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
|
|
///
|
|
void ISel::visitPHINode(PHINode &PN) {
|
|
MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN));
|
|
|
|
for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
|
|
// FIXME: This will put constants after the PHI nodes in the block, which
|
|
// is invalid. They should be put inline into the PHI node eventually.
|
|
//
|
|
MI->addRegOperand(getReg(PN.getIncomingValue(i)));
|
|
MI->addPCDispOperand(PN.getIncomingBlock(i));
|
|
}
|
|
}
|
|
|
|
|
|
/// createSimpleX86InstructionSelector - This pass converts an LLVM function
|
|
/// into a machine code representation is a very simple peep-hole fashion. The
|
|
/// generated code sucks but the implementation is nice and simple.
|
|
///
|
|
Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {
|
|
return new ISel(TM);
|
|
}
|