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630c5e06d6
Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
AsmParser | ||
Disassembler | ||
InstPrinter | ||
MCTargetDesc | ||
TargetInfo | ||
Utils | ||
AArch64.h | ||
AArch64.td | ||
AArch64AsmPrinter.cpp | ||
AArch64AsmPrinter.h | ||
AArch64BranchFixupPass.cpp | ||
AArch64CallingConv.td | ||
AArch64FrameLowering.cpp | ||
AArch64FrameLowering.h | ||
AArch64InstrFormats.td | ||
AArch64InstrInfo.cpp | ||
AArch64InstrInfo.h | ||
AArch64InstrInfo.td | ||
AArch64InstrNEON.td | ||
AArch64ISelDAGToDAG.cpp | ||
AArch64ISelLowering.cpp | ||
AArch64ISelLowering.h | ||
AArch64MachineFunctionInfo.cpp | ||
AArch64MachineFunctionInfo.h | ||
AArch64MCInstLower.cpp | ||
AArch64RegisterInfo.cpp | ||
AArch64RegisterInfo.h | ||
AArch64RegisterInfo.td | ||
AArch64Schedule.td | ||
AArch64SelectionDAGInfo.cpp | ||
AArch64SelectionDAGInfo.h | ||
AArch64Subtarget.cpp | ||
AArch64Subtarget.h | ||
AArch64TargetMachine.cpp | ||
AArch64TargetMachine.h | ||
AArch64TargetObjectFile.cpp | ||
AArch64TargetObjectFile.h | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
Makefile | ||
README.txt |
This file will contain changes that need to be made before AArch64 can become an officially supported target. Currently a placeholder.