Evan Cheng 4a03775777 For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55807 91177308-0d34-0410-b5e6-96231b3b80d8		2008-09-04 22:59:58 +00:00
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Alpha	allow this to pass.	2008-08-29 17:18:26 +00:00
ARM
CBackend
CellSPU	Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR	2008-08-31 02:59:23 +00:00
CPP
Generic	Turn this legalize types test on.	2008-09-01 12:00:55 +00:00
IA64
Mips
PowerPC	Testcases for ppc atomics.	2008-08-30 00:54:31 +00:00
SPARC
X86	For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.	2008-09-04 22:59:58 +00:00