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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
106 lines
2.3 KiB
LLVM
106 lines
2.3 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
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define void @foo1(i16* %p, i16* %r) nounwind {
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entry:
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%v = load i16, i16* %p, align 1
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store i16 %v, i16* %r, align 1
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ret void
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; CHECK: @foo1
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; CHECK: lhz
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; CHECK: sth
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; CHECK-VSX: @foo1
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; CHECK-VSX: lhz
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; CHECK-VSX: sth
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}
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define void @foo2(i32* %p, i32* %r) nounwind {
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entry:
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%v = load i32, i32* %p, align 1
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store i32 %v, i32* %r, align 1
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ret void
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; CHECK: @foo2
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; CHECK: lwz
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; CHECK: stw
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; CHECK-VSX: @foo2
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; CHECK-VSX: lwz
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; CHECK-VSX: stw
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}
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define void @foo3(i64* %p, i64* %r) nounwind {
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entry:
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%v = load i64, i64* %p, align 1
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store i64 %v, i64* %r, align 1
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ret void
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; CHECK: @foo3
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; CHECK: ld
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; CHECK: std
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; CHECK-VSX: @foo3
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; CHECK-VSX: ld
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; CHECK-VSX: std
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}
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define void @foo4(float* %p, float* %r) nounwind {
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entry:
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%v = load float, float* %p, align 1
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store float %v, float* %r, align 1
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ret void
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; CHECK: @foo4
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; CHECK: lfs
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; CHECK: stfs
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; CHECK-VSX: @foo4
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; CHECK-VSX: lfs
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; CHECK-VSX: stfs
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}
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define void @foo5(double* %p, double* %r) nounwind {
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entry:
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%v = load double, double* %p, align 1
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store double %v, double* %r, align 1
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ret void
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; CHECK: @foo5
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; CHECK: lfd
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; CHECK: stfd
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; CHECK-VSX: @foo5
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; CHECK-VSX: lxsdx
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; CHECK-VSX: stxsdx
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}
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define void @foo6(<4 x float>* %p, <4 x float>* %r) nounwind {
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entry:
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%v = load <4 x float>, <4 x float>* %p, align 1
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store <4 x float> %v, <4 x float>* %r, align 1
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ret void
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; These loads and stores are legalized into aligned loads and stores
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; using aligned stack slots.
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; CHECK: @foo6
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; CHECK-DAG: ld
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; CHECK-DAG: ld
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; CHECK-DAG: stdx
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; CHECK: stdx
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; For VSX on P7, unaligned loads and stores are preferable to aligned
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; stack slots, but lvsl/vperm is better still. (On P8 lxvw4x is preferable.)
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; Using unaligned stxvw4x is preferable on both machines.
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; CHECK-VSX: @foo6
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; CHECK-VSX-DAG: lvsl
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; CHECK-VSX-DAG: lvx
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; CHECK-VSX-DAG: lvx
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; CHECK-VSX: vperm
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; CHECK-VSX: stxvw4x
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}
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