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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
1.9 KiB
LLVM
41 lines
1.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare float @llvm.minnum.f32(float, float) nounwind readnone
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; SI-LABEL: {{^}}test_fmin3_olt_0:
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; SI: buffer_load_dword [[REGC:v[0-9]+]]
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; SI: buffer_load_dword [[REGB:v[0-9]+]]
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; SI: buffer_load_dword [[REGA:v[0-9]+]]
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; SI: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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define void @test_fmin3_olt_0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
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%a = load float, float addrspace(1)* %aptr, align 4
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%b = load float, float addrspace(1)* %bptr, align 4
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%c = load float, float addrspace(1)* %cptr, align 4
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%f0 = call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
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%f1 = call float @llvm.minnum.f32(float %f0, float %c) nounwind readnone
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store float %f1, float addrspace(1)* %out, align 4
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ret void
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}
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; Commute operand of second fmin
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; SI-LABEL: {{^}}test_fmin3_olt_1:
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; SI: buffer_load_dword [[REGB:v[0-9]+]]
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; SI: buffer_load_dword [[REGA:v[0-9]+]]
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; SI: buffer_load_dword [[REGC:v[0-9]+]]
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; SI: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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define void @test_fmin3_olt_1(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
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%a = load float, float addrspace(1)* %aptr, align 4
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%b = load float, float addrspace(1)* %bptr, align 4
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%c = load float, float addrspace(1)* %cptr, align 4
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%f0 = call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
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%f1 = call float @llvm.minnum.f32(float %c, float %f0) nounwind readnone
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store float %f1, float addrspace(1)* %out, align 4
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ret void
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}
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