llvm-6502/test/CodeGen/Thumb2/tpsoft.ll
Peter Collingbourne f86c29ea2c ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets.
This makes it more likely that we can use the 16-bit push and pop instructions
on Thumb-2, saving around 4 bytes per function.

Differential Revision: http://reviews.llvm.org/D9165

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235637 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 20:31:26 +00:00

55 lines
1.8 KiB
LLVM

; RUN: llc %s -mtriple=thumbv7-linux-gnueabi -o - | \
; RUN: FileCheck -check-prefix=ELFASM %s
; RUN: llc %s -mtriple=thumbebv7-linux-gnueabi -o - | \
; RUN: FileCheck -check-prefix=ELFASM %s
; RUN: llc %s -mtriple=thumbv7-linux-gnueabi -filetype=obj -o - | \
; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=ELFOBJ -check-prefix=ELFOBJ-LE %s
; RUN: llc %s -mtriple=thumbebv7-linux-gnueabi -filetype=obj -o - | \
; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=ELFOBJ -check-prefix=ELFOBJ-BE %s
;; Make sure that bl __aeabi_read_tp is materialized and fixed up correctly
;; in the obj case.
@i = external thread_local global i32
@a = external global i8
@b = external global [10 x i8]
define arm_aapcs_vfpcc i32 @main() nounwind {
entry:
%0 = load i32, i32* @i, align 4
switch i32 %0, label %bb2 [
i32 12, label %bb
i32 13, label %bb1
]
bb: ; preds = %entry
%1 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind
ret i32 %1
; ELFASM: bl __aeabi_read_tp
; ELFOBJ: Sections [
; ELFOBJ: Section {
; ELFOBJ: Name: .text
; ELFOBJ-LE: SectionData (
;;; BL __aeabi_read_tp is ---+
;;; V
; ELFOBJ-LE-NEXT: 0000: 80B50E48 78440168 FFF7FEFF 40580D28
; ELFOBJ-BE: SectionData (
;;; BL __aeabi_read_tp is ---+
;;; V
; ELFOBJ-BE-NEXT: 0000: B580480E 44786801 F7FFFFFE 5840280D
bb1: ; preds = %entry
%2 = tail call arm_aapcs_vfpcc i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind
ret i32 %2
bb2: ; preds = %entry
ret i32 -1
}
declare arm_aapcs_vfpcc i32 @foo(i8*)
declare arm_aapcs_vfpcc i32 @bar(i32*)