mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 20:29:21 +00:00
5ffe38ef6a
fixups yet, and doesn't handle actually encoding operand values, but this is enough for llc -show-mc-encoding to show the base instruction encoding information, e.g.: mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6] stw r0, 8(r1) ; encoding: [0x90,0x00,0x00,0x00] stwu r1, -64(r1) ; encoding: [0x94,0x00,0x00,0x00] Ltmp0: lhz r4, 4(r3) ; encoding: [0xa0,0x00,0x00,0x00] cmplwi cr0, r4, 8 ; encoding: [0x28,0x00,0x00,0x00] beq cr0, LBB0_2 ; encoding: [0x40,0x00,0x00,0x00] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119116 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
856 B
Makefile
25 lines
856 B
Makefile
##===- lib/Target/PowerPC/Makefile -------------------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file is distributed under the University of Illinois Open Source
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# License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = LLVMPowerPCCodeGen
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TARGET = PPC
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
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PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
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PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
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PPCGenInstrInfo.inc PPCGenDAGISel.inc \
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PPCGenSubtarget.inc PPCGenCallingConv.inc \
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PPCGenMCCodeEmitter.inc
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DIRS = InstPrinter TargetInfo
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include $(LEVEL)/Makefile.common
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