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https://github.com/c64scene-ar/llvm-6502.git
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Found by the Clang static analyzer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224586 91177308-0d34-0410-b5e6-96231b3b80d8
588 lines
22 KiB
C++
588 lines
22 KiB
C++
//===-- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-1 implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#include "Thumb1RegisterInfo.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMSubtarget.h"
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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extern cl::opt<bool> ReuseFrameIndexVals;
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}
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using namespace llvm;
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Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMSubtarget &sti)
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: ARMBaseRegisterInfo(sti) {
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}
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const TargetRegisterClass*
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Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
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const {
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if (ARM::tGPRRegClass.hasSubClassEq(RC))
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return &ARM::tGPRRegClass;
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return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC);
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}
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const TargetRegisterClass *
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Thumb1RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
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const {
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return &ARM::tGPRRegClass;
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}
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void
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Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned SubIdx,
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int Val,
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned MIFlags) const {
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assert((isARMLowRegister(DestReg) ||
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isVirtualRegister(DestReg)) &&
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"Thumb1 does not have ldr to high register");
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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MachineConstantPool *ConstantPool = MF.getConstantPool();
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const Constant *C = ConstantInt::get(
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Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
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unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
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.addReg(DestReg, getDefRegState(true), SubIdx)
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.addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
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.setMIFlags(MIFlags);
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}
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/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
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/// in a register using mov / mvn sequences or load the immediate from a
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/// constpool entry.
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static
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void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned BaseReg,
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int NumBytes, bool CanChangeCC,
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const TargetInstrInfo &TII,
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const ARMBaseRegisterInfo& MRI,
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unsigned MIFlags = MachineInstr::NoFlags) {
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MachineFunction &MF = *MBB.getParent();
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bool isHigh = !isARMLowRegister(DestReg) ||
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(BaseReg != 0 && !isARMLowRegister(BaseReg));
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bool isSub = false;
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// Subtract doesn't have high register version. Load the negative value
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// if either base or dest register is a high register. Also, if do not
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// issue sub as part of the sequence if condition register is to be
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// preserved.
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if (NumBytes < 0 && !isHigh && CanChangeCC) {
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isSub = true;
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NumBytes = -NumBytes;
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}
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unsigned LdReg = DestReg;
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if (DestReg == ARM::SP)
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assert(BaseReg == ARM::SP && "Unexpected!");
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if (!isARMLowRegister(DestReg) && !MRI.isVirtualRegister(DestReg))
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LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
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if (NumBytes <= 255 && NumBytes >= 0 && CanChangeCC) {
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
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.addImm(NumBytes).setMIFlags(MIFlags);
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} else if (NumBytes < 0 && NumBytes >= -255 && CanChangeCC) {
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
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.addImm(NumBytes).setMIFlags(MIFlags);
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
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.addReg(LdReg, RegState::Kill).setMIFlags(MIFlags);
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} else
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MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes,
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ARMCC::AL, 0, MIFlags);
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// Emit add / sub.
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int Opc = (isSub) ? ARM::tSUBrr : ((isHigh || !CanChangeCC) ? ARM::tADDhirr
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: ARM::tADDrr);
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
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if (Opc != ARM::tADDhirr)
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MIB = AddDefaultT1CC(MIB);
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if (DestReg == ARM::SP || isSub)
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MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
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else
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MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
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AddDefaultPred(MIB);
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}
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/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in Thumb code. Tries a series of ADDs or
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/// SUBs first, and uses a constant pool value if the instruction sequence would
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/// be too long. This is allowed to modify the condition flags.
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void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned BaseReg,
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int NumBytes, const TargetInstrInfo &TII,
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const ARMBaseRegisterInfo& MRI,
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unsigned MIFlags) {
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bool isSub = NumBytes < 0;
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unsigned Bytes = (unsigned)NumBytes;
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if (isSub) Bytes = -NumBytes;
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int CopyOpc = 0;
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unsigned CopyBits = 0;
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unsigned CopyScale = 1;
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bool CopyNeedsCC = false;
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int ExtraOpc = 0;
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unsigned ExtraBits = 0;
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unsigned ExtraScale = 1;
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bool ExtraNeedsCC = false;
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// Strategy:
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// We need to select two types of instruction, maximizing the available
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// immediate range of each. The instructions we use will depend on whether
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// DestReg and BaseReg are low, high or the stack pointer.
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// * CopyOpc - DestReg = BaseReg + imm
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// This will be emitted once if DestReg != BaseReg, and never if
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// DestReg == BaseReg.
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// * ExtraOpc - DestReg = DestReg + imm
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// This will be emitted as many times as necessary to add the
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// full immediate.
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// If the immediate ranges of these instructions are not large enough to cover
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// NumBytes with a reasonable number of instructions, we fall back to using a
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// value loaded from a constant pool.
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if (DestReg == ARM::SP) {
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if (BaseReg == ARM::SP) {
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// sp -> sp
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// Already in right reg, no copy needed
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} else {
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// low -> sp or high -> sp
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CopyOpc = ARM::tMOVr;
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CopyBits = 0;
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}
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ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi;
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ExtraBits = 7;
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ExtraScale = 4;
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} else if (isARMLowRegister(DestReg)) {
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if (BaseReg == ARM::SP) {
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// sp -> low
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assert(!isSub && "Thumb1 does not have tSUBrSPi");
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CopyOpc = ARM::tADDrSPi;
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CopyBits = 8;
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CopyScale = 4;
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} else if (DestReg == BaseReg) {
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// low -> same low
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// Already in right reg, no copy needed
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} else if (isARMLowRegister(BaseReg)) {
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// low -> different low
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CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3;
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CopyBits = 3;
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CopyNeedsCC = true;
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} else {
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// high -> low
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CopyOpc = ARM::tMOVr;
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CopyBits = 0;
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}
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ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
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ExtraBits = 8;
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ExtraNeedsCC = true;
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} else /* DestReg is high */ {
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if (DestReg == BaseReg) {
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// high -> same high
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// Already in right reg, no copy needed
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} else {
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// {low,high,sp} -> high
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CopyOpc = ARM::tMOVr;
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CopyBits = 0;
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}
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ExtraOpc = 0;
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}
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// We could handle an unaligned immediate with an unaligned copy instruction
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// and an aligned extra instruction, but this case is not currently needed.
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assert(((Bytes & 3) == 0 || ExtraScale == 1) &&
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"Unaligned offset, but all instructions require alignment");
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unsigned CopyRange = ((1 << CopyBits) - 1) * CopyScale;
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// If we would emit the copy with an immediate of 0, just use tMOVr.
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if (CopyOpc && Bytes < CopyScale) {
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CopyOpc = ARM::tMOVr;
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CopyScale = 1;
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CopyNeedsCC = false;
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CopyRange = 0;
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}
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unsigned ExtraRange = ((1 << ExtraBits) - 1) * ExtraScale; // per instruction
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unsigned RequiredCopyInstrs = CopyOpc ? 1 : 0;
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unsigned RangeAfterCopy = (CopyRange > Bytes) ? 0 : (Bytes - CopyRange);
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// We could handle this case when the copy instruction does not require an
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// aligned immediate, but we do not currently do this.
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assert(RangeAfterCopy % ExtraScale == 0 &&
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"Extra instruction requires immediate to be aligned");
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unsigned RequiredExtraInstrs;
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if (ExtraRange)
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RequiredExtraInstrs = RoundUpToAlignment(RangeAfterCopy, ExtraRange) / ExtraRange;
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else if (RangeAfterCopy > 0)
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// We need an extra instruction but none is available
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RequiredExtraInstrs = 1000000;
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else
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RequiredExtraInstrs = 0;
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unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs;
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unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
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// Use a constant pool, if the sequence of ADDs/SUBs is too expensive.
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if (RequiredInstrs > Threshold) {
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emitThumbRegPlusImmInReg(MBB, MBBI, dl,
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DestReg, BaseReg, NumBytes, true,
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TII, MRI, MIFlags);
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return;
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}
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// Emit zero or one copy instructions
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if (CopyOpc) {
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unsigned CopyImm = std::min(Bytes, CopyRange) / CopyScale;
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Bytes -= CopyImm * CopyScale;
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
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if (CopyNeedsCC)
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(BaseReg, RegState::Kill);
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if (CopyOpc != ARM::tMOVr) {
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MIB.addImm(CopyImm);
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}
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AddDefaultPred(MIB.setMIFlags(MIFlags));
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BaseReg = DestReg;
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}
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// Emit zero or more in-place add/sub instructions
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while (Bytes) {
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unsigned ExtraImm = std::min(Bytes, ExtraRange) / ExtraScale;
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Bytes -= ExtraImm * ExtraScale;
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg);
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if (ExtraNeedsCC)
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(BaseReg).addImm(ExtraImm);
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MIB = AddDefaultPred(MIB);
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MIB.setMIFlags(MIFlags);
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}
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}
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static void removeOperands(MachineInstr &MI, unsigned i) {
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unsigned Op = i;
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for (unsigned e = MI.getNumOperands(); i != e; ++i)
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MI.RemoveOperand(Op);
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}
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/// convertToNonSPOpcode - Change the opcode to the non-SP version, because
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/// we're replacing the frame index with a non-SP register.
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static unsigned convertToNonSPOpcode(unsigned Opcode) {
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switch (Opcode) {
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case ARM::tLDRspi:
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return ARM::tLDRi;
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case ARM::tSTRspi:
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return ARM::tSTRi;
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}
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return Opcode;
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}
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bool Thumb1RegisterInfo::
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rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const ARMBaseInstrInfo &TII) const {
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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MachineInstrBuilder MIB(*MBB.getParent(), &MI);
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unsigned Opcode = MI.getOpcode();
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const MCInstrDesc &Desc = MI.getDesc();
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unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
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if (Opcode == ARM::tADDframe) {
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Offset += MI.getOperand(FrameRegIdx+1).getImm();
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unsigned DestReg = MI.getOperand(0).getReg();
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emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
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*this);
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MBB.erase(II);
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return true;
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} else {
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if (AddrMode != ARMII::AddrModeT1_s)
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llvm_unreachable("Unsupported addressing mode!");
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unsigned ImmIdx = FrameRegIdx + 1;
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int InstrOffs = MI.getOperand(ImmIdx).getImm();
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unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
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unsigned Scale = 4;
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Offset += InstrOffs * Scale;
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assert((Offset & (Scale - 1)) == 0 && "Can't encode this offset!");
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// Common case: small offset, fits into instruction.
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MachineOperand &ImmOp = MI.getOperand(ImmIdx);
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int ImmedOffset = Offset / Scale;
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unsigned Mask = (1 << NumBits) - 1;
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if ((unsigned)Offset <= Mask * Scale) {
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// Replace the FrameIndex with the frame register (e.g., sp).
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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ImmOp.ChangeToImmediate(ImmedOffset);
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// If we're using a register where sp was stored, convert the instruction
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// to the non-SP version.
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unsigned NewOpc = convertToNonSPOpcode(Opcode);
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if (NewOpc != Opcode && FrameReg != ARM::SP)
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MI.setDesc(TII.get(NewOpc));
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return true;
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}
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NumBits = 5;
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Mask = (1 << NumBits) - 1;
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// If this is a thumb spill / restore, we will be using a constpool load to
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// materialize the offset.
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if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
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ImmOp.ChangeToImmediate(0);
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} else {
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// Otherwise, it didn't fit. Pull in what we can to simplify the immed.
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ImmedOffset = ImmedOffset & Mask;
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ImmOp.ChangeToImmediate(ImmedOffset);
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Offset &= ~(Mask * Scale);
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}
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}
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return Offset == 0;
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}
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void Thumb1RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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int64_t Offset) const {
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const ARMBaseInstrInfo &TII =
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*static_cast<const ARMBaseInstrInfo *>(MI.getParent()
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->getParent()
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->getTarget()
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.getSubtargetImpl()
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->getInstrInfo());
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int Off = Offset; // ARM doesn't need the general 64-bit offsets
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unsigned i = 0;
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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bool Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);
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assert (Done && "Unable to resolve frame index!");
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(void)Done;
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}
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/// saveScavengerRegister - Spill the register so it can be used by the
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/// register scavenger. Return true.
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bool
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Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator &UseMI,
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const TargetRegisterClass *RC,
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unsigned Reg) const {
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// Thumb1 can't use the emergency spill slot on the stack because
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// ldr/str immediate offsets must be positive, and if we're referencing
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// off the frame pointer (if, for example, there are alloca() calls in
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// the function, the offset will be negative. Use R12 instead since that's
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// a call clobbered register that we know won't be used in Thumb1 mode.
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const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
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DebugLoc DL;
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AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
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.addReg(ARM::R12, RegState::Define)
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.addReg(Reg, RegState::Kill));
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// The UseMI is where we would like to restore the register. If there's
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// interference with R12 before then, however, we'll need to restore it
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// before that instead and adjust the UseMI.
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bool done = false;
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for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
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if (II->isDebugValue())
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continue;
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// If this instruction affects R12, adjust our restore point.
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for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = II->getOperand(i);
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if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {
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UseMI = II;
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done = true;
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break;
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}
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if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
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TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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continue;
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if (MO.getReg() == ARM::R12) {
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UseMI = II;
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done = true;
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break;
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}
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}
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}
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// Restore the register from R12
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AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
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addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
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return true;
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}
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void
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Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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unsigned VReg = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
|
|
MachineFunction &MF = *MBB.getParent();
|
|
const ARMBaseInstrInfo &TII =
|
|
*static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
DebugLoc dl = MI.getDebugLoc();
|
|
MachineInstrBuilder MIB(*MBB.getParent(), &MI);
|
|
|
|
unsigned FrameReg = ARM::SP;
|
|
int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
|
|
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
|
|
MF.getFrameInfo()->getStackSize() + SPAdj;
|
|
|
|
if (MF.getFrameInfo()->hasVarSizedObjects()) {
|
|
assert(SPAdj == 0 && MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
|
|
"Unexpected");
|
|
// There are alloca()'s in this function, must reference off the frame
|
|
// pointer or base pointer instead.
|
|
if (!hasBasePointer(MF)) {
|
|
FrameReg = getFrameRegister(MF);
|
|
Offset -= AFI->getFramePtrSpillOffset();
|
|
} else
|
|
FrameReg = BasePtr;
|
|
}
|
|
|
|
// PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
|
|
// call frame setup/destroy instructions have already been eliminated. That
|
|
// means the stack pointer cannot be used to access the emergency spill slot
|
|
// when !hasReservedCallFrame().
|
|
#ifndef NDEBUG
|
|
if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
|
|
assert(MF.getTarget()
|
|
.getSubtargetImpl()
|
|
->getFrameLowering()
|
|
->hasReservedCallFrame(MF) &&
|
|
"Cannot use SP to access the emergency spill slot in "
|
|
"functions without a reserved call frame");
|
|
assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
|
|
"Cannot use SP to access the emergency spill slot in "
|
|
"functions with variable sized frame objects");
|
|
}
|
|
#endif // NDEBUG
|
|
|
|
// Special handling of dbg_value instructions.
|
|
if (MI.isDebugValue()) {
|
|
MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);
|
|
MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
|
|
return;
|
|
}
|
|
|
|
// Modify MI as necessary to handle as much of 'Offset' as possible
|
|
assert(AFI->isThumbFunction() &&
|
|
"This eliminateFrameIndex only supports Thumb1!");
|
|
if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
|
|
return;
|
|
|
|
// If we get here, the immediate doesn't fit into the instruction. We folded
|
|
// as much as possible above, handle the rest, providing a register that is
|
|
// SP+LargeImm.
|
|
assert(Offset && "This code isn't needed if offset already handled!");
|
|
|
|
unsigned Opcode = MI.getOpcode();
|
|
|
|
// Remove predicate first.
|
|
int PIdx = MI.findFirstPredOperandIdx();
|
|
if (PIdx != -1)
|
|
removeOperands(MI, PIdx);
|
|
|
|
if (MI.mayLoad()) {
|
|
// Use the destination register to materialize sp + offset.
|
|
unsigned TmpReg = MI.getOperand(0).getReg();
|
|
bool UseRR = false;
|
|
if (Opcode == ARM::tLDRspi) {
|
|
if (FrameReg == ARM::SP)
|
|
emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
|
|
Offset, false, TII, *this);
|
|
else {
|
|
emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
|
|
UseRR = true;
|
|
}
|
|
} else {
|
|
emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
|
|
*this);
|
|
}
|
|
|
|
MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
|
|
MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
|
|
if (UseRR)
|
|
// Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
|
|
// register. The offset is already handled in the vreg value.
|
|
MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
|
|
false);
|
|
} else if (MI.mayStore()) {
|
|
VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
|
|
bool UseRR = false;
|
|
|
|
if (Opcode == ARM::tSTRspi) {
|
|
if (FrameReg == ARM::SP)
|
|
emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
|
|
Offset, false, TII, *this);
|
|
else {
|
|
emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
|
|
UseRR = true;
|
|
}
|
|
} else
|
|
emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
|
|
*this);
|
|
MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
|
|
MI.getOperand(FIOperandNum).ChangeToRegister(VReg, false, false, true);
|
|
if (UseRR)
|
|
// Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
|
|
// register. The offset is already handled in the vreg value.
|
|
MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
|
|
false);
|
|
} else {
|
|
llvm_unreachable("Unexpected opcode!");
|
|
}
|
|
|
|
// Add predicate back if it's needed.
|
|
if (MI.isPredicable())
|
|
AddDefaultPred(MIB);
|
|
}
|