Hal Finkel 958b670c34 [PowerPC] Add support for the CMPB instruction ... Newer POWER cores, and the A2, support the cmpb instruction. This instruction compares its operands, treating each of the 8 bytes in the GPRs separately, returning a 'mask' result of 0 (for false) or -1 (for true) in each byte. Code generation support is added, in the form of a PPCISelDAGToDAG DAG-preprocessing routine, that recognizes patterns close to what the instruction computes (either exactly, or related by a constant masking operation), and generates the cmpb instruction (along with any necessary constant masking operation). This can be expanded if use cases arise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225106 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-03 01:16:37 +00:00
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AArch64	Lower multiply-negate operation to mneg on AArch64	2014-12-22 13:38:58 +00:00
ARM	[ARM] Don't break alignment when combining base updates into load/stores.	2014-12-23 06:07:31 +00:00
CPP
Generic	CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.	2014-12-19 20:50:07 +00:00
Hexagon	[Hexagon] Adding reg-reg indexed load forms.	2014-12-30 18:58:47 +00:00
Inputs
Mips	[mips][microMIPS] Fix bugs related to atomic SC/LL instructions	2014-12-18 16:39:29 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add support for the CMPB instruction	2015-01-03 01:16:37 +00:00
R600	Enable (sext x) == C --> x == (trunc C) combine	2014-12-21 16:48:42 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	Revert "merge consecutive stores of extracted vector elements"	2014-12-31 00:40:28 +00:00
XCore