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Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
812 lines
27 KiB
C++
812 lines
27 KiB
C++
//===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64MachineFunctionInfo.h"
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#include "AArch64TargetMachine.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include <algorithm>
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#define GET_INSTRINFO_CTOR
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#include "AArch64GenInstrInfo.inc"
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using namespace llvm;
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AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
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: AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
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Subtarget(STI) {}
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void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned Opc = 0;
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unsigned ZeroReg = 0;
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if (DestReg == AArch64::XSP || SrcReg == AArch64::XSP) {
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// E.g. ADD xDst, xsp, #0 (, lsl #0)
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BuildMI(MBB, I, DL, get(AArch64::ADDxxi_lsl0_s), DestReg)
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.addReg(SrcReg)
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.addImm(0);
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return;
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} else if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
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// E.g. ADD wDST, wsp, #0 (, lsl #0)
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BuildMI(MBB, I, DL, get(AArch64::ADDwwi_lsl0_s), DestReg)
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.addReg(SrcReg)
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.addImm(0);
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return;
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} else if (DestReg == AArch64::NZCV) {
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assert(AArch64::GPR64RegClass.contains(SrcReg));
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// E.g. MSR NZCV, xDST
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BuildMI(MBB, I, DL, get(AArch64::MSRix))
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.addImm(A64SysReg::NZCV)
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.addReg(SrcReg);
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} else if (SrcReg == AArch64::NZCV) {
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assert(AArch64::GPR64RegClass.contains(DestReg));
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// E.g. MRS xDST, NZCV
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BuildMI(MBB, I, DL, get(AArch64::MRSxi), DestReg)
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.addImm(A64SysReg::NZCV);
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} else if (AArch64::GPR64RegClass.contains(DestReg)) {
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assert(AArch64::GPR64RegClass.contains(SrcReg));
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Opc = AArch64::ORRxxx_lsl;
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ZeroReg = AArch64::XZR;
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} else if (AArch64::GPR32RegClass.contains(DestReg)) {
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assert(AArch64::GPR32RegClass.contains(SrcReg));
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Opc = AArch64::ORRwww_lsl;
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ZeroReg = AArch64::WZR;
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} else if (AArch64::FPR32RegClass.contains(DestReg)) {
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assert(AArch64::FPR32RegClass.contains(SrcReg));
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BuildMI(MBB, I, DL, get(AArch64::FMOVss), DestReg)
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.addReg(SrcReg);
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return;
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} else if (AArch64::FPR64RegClass.contains(DestReg)) {
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assert(AArch64::FPR64RegClass.contains(SrcReg));
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BuildMI(MBB, I, DL, get(AArch64::FMOVdd), DestReg)
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.addReg(SrcReg);
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return;
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} else if (AArch64::FPR128RegClass.contains(DestReg)) {
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assert(AArch64::FPR128RegClass.contains(SrcReg));
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// FIXME: there's no good way to do this, at least without NEON:
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// + There's no single move instruction for q-registers
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// + We can't create a spill slot and use normal STR/LDR because stack
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// allocation has already happened
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// + We can't go via X-registers with FMOV because register allocation has
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// already happened.
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// This may not be efficient, but at least it works.
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BuildMI(MBB, I, DL, get(AArch64::LSFP128_PreInd_STR), AArch64::XSP)
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.addReg(SrcReg)
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.addReg(AArch64::XSP)
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.addImm(0x1ff & -16);
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BuildMI(MBB, I, DL, get(AArch64::LSFP128_PostInd_LDR), DestReg)
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.addReg(AArch64::XSP, RegState::Define)
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.addReg(AArch64::XSP)
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.addImm(16);
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return;
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} else {
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llvm_unreachable("Unknown register class in copyPhysReg");
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}
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// E.g. ORR xDst, xzr, xSrc, lsl #0
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BuildMI(MBB, I, DL, get(Opc), DestReg)
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.addReg(ZeroReg)
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.addReg(SrcReg)
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.addImm(0);
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}
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/// Does the Opcode represent a conditional branch that we can remove and re-add
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/// at the end of a basic block?
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static bool isCondBranch(unsigned Opc) {
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return Opc == AArch64::Bcc || Opc == AArch64::CBZw || Opc == AArch64::CBZx ||
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Opc == AArch64::CBNZw || Opc == AArch64::CBNZx ||
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Opc == AArch64::TBZwii || Opc == AArch64::TBZxii ||
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Opc == AArch64::TBNZwii || Opc == AArch64::TBNZxii;
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}
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/// Takes apart a given conditional branch MachineInstr (see isCondBranch),
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/// setting TBB to the destination basic block and populating the Cond vector
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/// with data necessary to recreate the conditional branch at a later
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/// date. First element will be the opcode, and subsequent ones define the
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/// conditions being branched on in an instruction-specific manner.
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static void classifyCondBranch(MachineInstr *I, MachineBasicBlock *&TBB,
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SmallVectorImpl<MachineOperand> &Cond) {
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switch(I->getOpcode()) {
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case AArch64::Bcc:
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case AArch64::CBZw:
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case AArch64::CBZx:
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case AArch64::CBNZw:
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case AArch64::CBNZx:
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// These instructions just have one predicate operand in position 0 (either
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// a condition code or a register being compared).
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Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
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Cond.push_back(I->getOperand(0));
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TBB = I->getOperand(1).getMBB();
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return;
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case AArch64::TBZwii:
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case AArch64::TBZxii:
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case AArch64::TBNZwii:
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case AArch64::TBNZxii:
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// These have two predicate operands: a register and a bit position.
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Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
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Cond.push_back(I->getOperand(0));
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Cond.push_back(I->getOperand(1));
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TBB = I->getOperand(2).getMBB();
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return;
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default:
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llvm_unreachable("Unknown conditional branch to classify");
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}
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}
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bool
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AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin())
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return false;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return false;
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--I;
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}
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if (!isUnpredicatedTerminator(I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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unsigned LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (LastOpc == AArch64::Bimm) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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if (isCondBranch(LastOpc)) {
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classifyCondBranch(LastInst, TBB, Cond);
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return false;
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}
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return true; // Can't handle indirect branch.
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}
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// Get the instruction before it if it is a terminator.
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MachineInstr *SecondLastInst = I;
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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// If AllowModify is true and the block ends with two or more unconditional
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// branches, delete all but the first unconditional branch.
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if (AllowModify && LastOpc == AArch64::Bimm) {
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while (SecondLastOpc == AArch64::Bimm) {
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LastInst->eraseFromParent();
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LastInst = SecondLastInst;
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LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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// Return now the only terminator is an unconditional branch.
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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} else {
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SecondLastInst = I;
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SecondLastOpc = SecondLastInst->getOpcode();
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}
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}
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}
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
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return true;
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// If the block ends with a B and a Bcc, handle it.
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if (LastOpc == AArch64::Bimm) {
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if (SecondLastOpc == AArch64::Bcc) {
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TBB = SecondLastInst->getOperand(1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(AArch64::Bcc));
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Cond.push_back(SecondLastInst->getOperand(0));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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} else if (isCondBranch(SecondLastOpc)) {
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classifyCondBranch(SecondLastInst, TBB, Cond);
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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}
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// If the block ends with two unconditional branches, handle it. The second
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// one is not executed, so remove it.
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if (SecondLastOpc == AArch64::Bimm && LastOpc == AArch64::Bimm) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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bool AArch64InstrInfo::ReverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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switch (Cond[0].getImm()) {
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case AArch64::Bcc: {
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A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(Cond[1].getImm());
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CC = A64InvertCondCode(CC);
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Cond[1].setImm(CC);
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return false;
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}
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case AArch64::CBZw:
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Cond[0].setImm(AArch64::CBNZw);
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return false;
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case AArch64::CBZx:
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Cond[0].setImm(AArch64::CBNZx);
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return false;
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case AArch64::CBNZw:
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Cond[0].setImm(AArch64::CBZw);
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return false;
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case AArch64::CBNZx:
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Cond[0].setImm(AArch64::CBZx);
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return false;
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case AArch64::TBZwii:
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Cond[0].setImm(AArch64::TBNZwii);
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return false;
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case AArch64::TBZxii:
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Cond[0].setImm(AArch64::TBNZxii);
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return false;
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case AArch64::TBNZwii:
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Cond[0].setImm(AArch64::TBZwii);
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return false;
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case AArch64::TBNZxii:
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Cond[0].setImm(AArch64::TBZxii);
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return false;
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default:
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llvm_unreachable("Unknown branch type");
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}
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}
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unsigned
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AArch64InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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if (FBB == 0 && Cond.empty()) {
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BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(TBB);
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return 1;
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} else if (FBB == 0) {
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MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
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for (int i = 1, e = Cond.size(); i != e; ++i)
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MIB.addOperand(Cond[i]);
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MIB.addMBB(TBB);
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return 1;
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}
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MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
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for (int i = 1, e = Cond.size(); i != e; ++i)
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MIB.addOperand(Cond[i]);
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MIB.addMBB(TBB);
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BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(FBB);
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return 2;
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}
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unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return 0;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return 0;
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--I;
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}
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if (I->getOpcode() != AArch64::Bimm && !isCondBranch(I->getOpcode()))
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return 1;
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--I;
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if (!isCondBranch(I->getOpcode()))
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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bool
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AArch64InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const {
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MachineInstr &MI = *MBBI;
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MachineBasicBlock &MBB = *MI.getParent();
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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case AArch64::TLSDESC_BLRx: {
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MachineInstr *NewMI =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), get(AArch64::TLSDESCCALL))
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.addOperand(MI.getOperand(1));
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MI.setDesc(get(AArch64::BLRx));
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llvm::finalizeBundle(MBB, NewMI, *++MBBI);
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return true;
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}
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default:
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return false;
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}
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return false;
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}
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void
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AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill,
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int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL = MBB.findDebugLoc(MBBI);
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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unsigned Align = MFI.getObjectAlignment(FrameIdx);
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MachineMemOperand *MMO
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= MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
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MachineMemOperand::MOStore,
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MFI.getObjectSize(FrameIdx),
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Align);
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unsigned StoreOp = 0;
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if (RC->hasType(MVT::i64) || RC->hasType(MVT::i32)) {
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switch(RC->getSize()) {
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case 4: StoreOp = AArch64::LS32_STR; break;
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case 8: StoreOp = AArch64::LS64_STR; break;
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default:
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llvm_unreachable("Unknown size for regclass");
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}
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} else {
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assert((RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
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RC->hasType(MVT::f128))
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&& "Expected integer or floating type for store");
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switch (RC->getSize()) {
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case 4: StoreOp = AArch64::LSFP32_STR; break;
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case 8: StoreOp = AArch64::LSFP64_STR; break;
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case 16: StoreOp = AArch64::LSFP128_STR; break;
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default:
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llvm_unreachable("Unknown size for regclass");
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}
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}
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MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(StoreOp));
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NewMI.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FrameIdx)
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.addImm(0)
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.addMemOperand(MMO);
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}
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void
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AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL = MBB.findDebugLoc(MBBI);
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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unsigned Align = MFI.getObjectAlignment(FrameIdx);
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MachineMemOperand *MMO
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= MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
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MachineMemOperand::MOLoad,
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MFI.getObjectSize(FrameIdx),
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Align);
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unsigned LoadOp = 0;
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if (RC->hasType(MVT::i64) || RC->hasType(MVT::i32)) {
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switch(RC->getSize()) {
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case 4: LoadOp = AArch64::LS32_LDR; break;
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case 8: LoadOp = AArch64::LS64_LDR; break;
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default:
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llvm_unreachable("Unknown size for regclass");
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}
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} else {
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assert((RC->hasType(MVT::f32) || RC->hasType(MVT::f64)
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|| RC->hasType(MVT::f128))
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&& "Expected integer or floating type for store");
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switch (RC->getSize()) {
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case 4: LoadOp = AArch64::LSFP32_LDR; break;
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case 8: LoadOp = AArch64::LSFP64_LDR; break;
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case 16: LoadOp = AArch64::LSFP128_LDR; break;
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default:
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llvm_unreachable("Unknown size for regclass");
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}
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}
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MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(LoadOp), DestReg);
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NewMI.addFrameIndex(FrameIdx)
|
|
.addImm(0)
|
|
.addMemOperand(MMO);
|
|
}
|
|
|
|
unsigned AArch64InstrInfo::estimateRSStackLimit(MachineFunction &MF) const {
|
|
unsigned Limit = (1 << 16) - 1;
|
|
for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
|
|
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
|
|
I != E; ++I) {
|
|
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
|
|
if (!I->getOperand(i).isFI()) continue;
|
|
|
|
// When using ADDxxi_lsl0_s to get the address of a stack object, 0xfff
|
|
// is the largest offset guaranteed to fit in the immediate offset.
|
|
if (I->getOpcode() == AArch64::ADDxxi_lsl0_s) {
|
|
Limit = std::min(Limit, 0xfffu);
|
|
break;
|
|
}
|
|
|
|
int AccessScale, MinOffset, MaxOffset;
|
|
getAddressConstraints(*I, AccessScale, MinOffset, MaxOffset);
|
|
Limit = std::min(Limit, static_cast<unsigned>(MaxOffset));
|
|
|
|
break; // At most one FI per instruction
|
|
}
|
|
}
|
|
}
|
|
|
|
return Limit;
|
|
}
|
|
void AArch64InstrInfo::getAddressConstraints(const MachineInstr &MI,
|
|
int &AccessScale, int &MinOffset,
|
|
int &MaxOffset) const {
|
|
switch (MI.getOpcode()) {
|
|
default: llvm_unreachable("Unkown load/store kind");
|
|
case TargetOpcode::DBG_VALUE:
|
|
AccessScale = 1;
|
|
MinOffset = INT_MIN;
|
|
MaxOffset = INT_MAX;
|
|
return;
|
|
case AArch64::LS8_LDR: case AArch64::LS8_STR:
|
|
case AArch64::LSFP8_LDR: case AArch64::LSFP8_STR:
|
|
case AArch64::LDRSBw:
|
|
case AArch64::LDRSBx:
|
|
AccessScale = 1;
|
|
MinOffset = 0;
|
|
MaxOffset = 0xfff;
|
|
return;
|
|
case AArch64::LS16_LDR: case AArch64::LS16_STR:
|
|
case AArch64::LSFP16_LDR: case AArch64::LSFP16_STR:
|
|
case AArch64::LDRSHw:
|
|
case AArch64::LDRSHx:
|
|
AccessScale = 2;
|
|
MinOffset = 0;
|
|
MaxOffset = 0xfff * AccessScale;
|
|
return;
|
|
case AArch64::LS32_LDR: case AArch64::LS32_STR:
|
|
case AArch64::LSFP32_LDR: case AArch64::LSFP32_STR:
|
|
case AArch64::LDRSWx:
|
|
case AArch64::LDPSWx:
|
|
AccessScale = 4;
|
|
MinOffset = 0;
|
|
MaxOffset = 0xfff * AccessScale;
|
|
return;
|
|
case AArch64::LS64_LDR: case AArch64::LS64_STR:
|
|
case AArch64::LSFP64_LDR: case AArch64::LSFP64_STR:
|
|
case AArch64::PRFM:
|
|
AccessScale = 8;
|
|
MinOffset = 0;
|
|
MaxOffset = 0xfff * AccessScale;
|
|
return;
|
|
case AArch64::LSFP128_LDR: case AArch64::LSFP128_STR:
|
|
AccessScale = 16;
|
|
MinOffset = 0;
|
|
MaxOffset = 0xfff * AccessScale;
|
|
return;
|
|
case AArch64::LSPair32_LDR: case AArch64::LSPair32_STR:
|
|
case AArch64::LSFPPair32_LDR: case AArch64::LSFPPair32_STR:
|
|
AccessScale = 4;
|
|
MinOffset = -0x40 * AccessScale;
|
|
MaxOffset = 0x3f * AccessScale;
|
|
return;
|
|
case AArch64::LSPair64_LDR: case AArch64::LSPair64_STR:
|
|
case AArch64::LSFPPair64_LDR: case AArch64::LSFPPair64_STR:
|
|
AccessScale = 8;
|
|
MinOffset = -0x40 * AccessScale;
|
|
MaxOffset = 0x3f * AccessScale;
|
|
return;
|
|
case AArch64::LSFPPair128_LDR: case AArch64::LSFPPair128_STR:
|
|
AccessScale = 16;
|
|
MinOffset = -0x40 * AccessScale;
|
|
MaxOffset = 0x3f * AccessScale;
|
|
return;
|
|
}
|
|
}
|
|
|
|
unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
|
|
const MCInstrDesc &MCID = MI.getDesc();
|
|
const MachineBasicBlock &MBB = *MI.getParent();
|
|
const MachineFunction &MF = *MBB.getParent();
|
|
const MCAsmInfo &MAI = *MF.getTarget().getMCAsmInfo();
|
|
|
|
if (MCID.getSize())
|
|
return MCID.getSize();
|
|
|
|
if (MI.getOpcode() == AArch64::INLINEASM)
|
|
return getInlineAsmLength(MI.getOperand(0).getSymbolName(), MAI);
|
|
|
|
if (MI.isLabel())
|
|
return 0;
|
|
|
|
switch (MI.getOpcode()) {
|
|
case TargetOpcode::BUNDLE:
|
|
return getInstBundleLength(MI);
|
|
case TargetOpcode::IMPLICIT_DEF:
|
|
case TargetOpcode::KILL:
|
|
case TargetOpcode::PROLOG_LABEL:
|
|
case TargetOpcode::EH_LABEL:
|
|
case TargetOpcode::DBG_VALUE:
|
|
return 0;
|
|
case AArch64::TLSDESCCALL:
|
|
return 0;
|
|
default:
|
|
llvm_unreachable("Unknown instruction class");
|
|
}
|
|
}
|
|
|
|
unsigned AArch64InstrInfo::getInstBundleLength(const MachineInstr &MI) const {
|
|
unsigned Size = 0;
|
|
MachineBasicBlock::const_instr_iterator I = MI;
|
|
MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
|
|
while (++I != E && I->isInsideBundle()) {
|
|
assert(!I->isBundle() && "No nested bundle!");
|
|
Size += getInstSizeInBytes(*I);
|
|
}
|
|
return Size;
|
|
}
|
|
|
|
bool llvm::rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
|
|
unsigned FrameReg, int &Offset,
|
|
const AArch64InstrInfo &TII) {
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
MachineFunction &MF = *MBB.getParent();
|
|
MachineFrameInfo &MFI = *MF.getFrameInfo();
|
|
|
|
MFI.getObjectOffset(FrameRegIdx);
|
|
llvm_unreachable("Unimplemented rewriteFrameIndex");
|
|
}
|
|
|
|
void llvm::emitRegUpdate(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
DebugLoc dl, const TargetInstrInfo &TII,
|
|
unsigned DstReg, unsigned SrcReg, unsigned ScratchReg,
|
|
int64_t NumBytes, MachineInstr::MIFlag MIFlags) {
|
|
if (NumBytes == 0 && DstReg == SrcReg)
|
|
return;
|
|
else if (abs64(NumBytes) & ~0xffffff) {
|
|
// Generically, we have to materialize the offset into a temporary register
|
|
// and subtract it. There are a couple of ways this could be done, for now
|
|
// we'll use a movz/movk or movn/movk sequence.
|
|
uint64_t Bits = static_cast<uint64_t>(abs64(NumBytes));
|
|
BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVZxii), ScratchReg)
|
|
.addImm(0xffff & Bits).addImm(0)
|
|
.setMIFlags(MIFlags);
|
|
|
|
Bits >>= 16;
|
|
if (Bits & 0xffff) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
|
|
.addReg(ScratchReg)
|
|
.addImm(0xffff & Bits).addImm(1)
|
|
.setMIFlags(MIFlags);
|
|
}
|
|
|
|
Bits >>= 16;
|
|
if (Bits & 0xffff) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
|
|
.addReg(ScratchReg)
|
|
.addImm(0xffff & Bits).addImm(2)
|
|
.setMIFlags(MIFlags);
|
|
}
|
|
|
|
Bits >>= 16;
|
|
if (Bits & 0xffff) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
|
|
.addReg(ScratchReg)
|
|
.addImm(0xffff & Bits).addImm(3)
|
|
.setMIFlags(MIFlags);
|
|
}
|
|
|
|
// ADD DST, SRC, xTMP (, lsl #0)
|
|
unsigned AddOp = NumBytes > 0 ? AArch64::ADDxxx_uxtx : AArch64::SUBxxx_uxtx;
|
|
BuildMI(MBB, MBBI, dl, TII.get(AddOp), DstReg)
|
|
.addReg(SrcReg, RegState::Kill)
|
|
.addReg(ScratchReg, RegState::Kill)
|
|
.addImm(0)
|
|
.setMIFlag(MIFlags);
|
|
return;
|
|
}
|
|
|
|
// Now we know that the adjustment can be done in at most two add/sub
|
|
// (immediate) instructions, which is always more efficient than a
|
|
// literal-pool load, or even a hypothetical movz/movk/add sequence
|
|
|
|
// Decide whether we're doing addition or subtraction
|
|
unsigned LowOp, HighOp;
|
|
if (NumBytes >= 0) {
|
|
LowOp = AArch64::ADDxxi_lsl0_s;
|
|
HighOp = AArch64::ADDxxi_lsl12_s;
|
|
} else {
|
|
LowOp = AArch64::SUBxxi_lsl0_s;
|
|
HighOp = AArch64::SUBxxi_lsl12_s;
|
|
NumBytes = abs64(NumBytes);
|
|
}
|
|
|
|
// If we're here, at the very least a move needs to be produced, which just
|
|
// happens to be materializable by an ADD.
|
|
if ((NumBytes & 0xfff) || NumBytes == 0) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(LowOp), DstReg)
|
|
.addReg(SrcReg, RegState::Kill)
|
|
.addImm(NumBytes & 0xfff)
|
|
.setMIFlag(MIFlags);
|
|
|
|
// Next update should use the register we've just defined.
|
|
SrcReg = DstReg;
|
|
}
|
|
|
|
if (NumBytes & 0xfff000) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(HighOp), DstReg)
|
|
.addReg(SrcReg, RegState::Kill)
|
|
.addImm(NumBytes >> 12)
|
|
.setMIFlag(MIFlags);
|
|
}
|
|
}
|
|
|
|
void llvm::emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
DebugLoc dl, const TargetInstrInfo &TII,
|
|
unsigned ScratchReg, int64_t NumBytes,
|
|
MachineInstr::MIFlag MIFlags) {
|
|
emitRegUpdate(MBB, MI, dl, TII, AArch64::XSP, AArch64::XSP, AArch64::X16,
|
|
NumBytes, MIFlags);
|
|
}
|
|
|
|
|
|
namespace {
|
|
struct LDTLSCleanup : public MachineFunctionPass {
|
|
static char ID;
|
|
LDTLSCleanup() : MachineFunctionPass(ID) {}
|
|
|
|
virtual bool runOnMachineFunction(MachineFunction &MF) {
|
|
AArch64MachineFunctionInfo* MFI
|
|
= MF.getInfo<AArch64MachineFunctionInfo>();
|
|
if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
|
|
// No point folding accesses if there isn't at least two.
|
|
return false;
|
|
}
|
|
|
|
MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
|
|
return VisitNode(DT->getRootNode(), 0);
|
|
}
|
|
|
|
// Visit the dominator subtree rooted at Node in pre-order.
|
|
// If TLSBaseAddrReg is non-null, then use that to replace any
|
|
// TLS_base_addr instructions. Otherwise, create the register
|
|
// when the first such instruction is seen, and then use it
|
|
// as we encounter more instructions.
|
|
bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
|
|
MachineBasicBlock *BB = Node->getBlock();
|
|
bool Changed = false;
|
|
|
|
// Traverse the current block.
|
|
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
|
|
++I) {
|
|
switch (I->getOpcode()) {
|
|
case AArch64::TLSDESC_BLRx:
|
|
// Make sure it's a local dynamic access.
|
|
if (!I->getOperand(1).isSymbol() ||
|
|
strcmp(I->getOperand(1).getSymbolName(), "_TLS_MODULE_BASE_"))
|
|
break;
|
|
|
|
if (TLSBaseAddrReg)
|
|
I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
|
|
else
|
|
I = SetRegister(I, &TLSBaseAddrReg);
|
|
Changed = true;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Visit the children of this block in the dominator tree.
|
|
for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
|
|
I != E; ++I) {
|
|
Changed |= VisitNode(*I, TLSBaseAddrReg);
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
// Replace the TLS_base_addr instruction I with a copy from
|
|
// TLSBaseAddrReg, returning the new instruction.
|
|
MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
|
|
unsigned TLSBaseAddrReg) {
|
|
MachineFunction *MF = I->getParent()->getParent();
|
|
const AArch64TargetMachine *TM =
|
|
static_cast<const AArch64TargetMachine *>(&MF->getTarget());
|
|
const AArch64InstrInfo *TII = TM->getInstrInfo();
|
|
|
|
// Insert a Copy from TLSBaseAddrReg to x0, which is where the rest of the
|
|
// code sequence assumes the address will be.
|
|
MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
|
|
TII->get(TargetOpcode::COPY),
|
|
AArch64::X0)
|
|
.addReg(TLSBaseAddrReg);
|
|
|
|
// Erase the TLS_base_addr instruction.
|
|
I->eraseFromParent();
|
|
|
|
return Copy;
|
|
}
|
|
|
|
// Create a virtal register in *TLSBaseAddrReg, and populate it by
|
|
// inserting a copy instruction after I. Returns the new instruction.
|
|
MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
|
|
MachineFunction *MF = I->getParent()->getParent();
|
|
const AArch64TargetMachine *TM =
|
|
static_cast<const AArch64TargetMachine *>(&MF->getTarget());
|
|
const AArch64InstrInfo *TII = TM->getInstrInfo();
|
|
|
|
// Create a virtual register for the TLS base address.
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
|
*TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
|
|
|
|
// Insert a copy from X0 to TLSBaseAddrReg for later.
|
|
MachineInstr *Next = I->getNextNode();
|
|
MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
|
|
TII->get(TargetOpcode::COPY),
|
|
*TLSBaseAddrReg)
|
|
.addReg(AArch64::X0);
|
|
|
|
return Copy;
|
|
}
|
|
|
|
virtual const char *getPassName() const {
|
|
return "Local Dynamic TLS Access Clean-up";
|
|
}
|
|
|
|
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
|
|
AU.setPreservesCFG();
|
|
AU.addRequired<MachineDominatorTree>();
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
};
|
|
}
|
|
|
|
char LDTLSCleanup::ID = 0;
|
|
FunctionPass*
|
|
llvm::createAArch64CleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
|