llvm-6502/lib/CodeGen/SelectionDAG
Bill Wendling 95b3955034 Assertion when using a 1-element vector for an add operation. Get the
real vector type in this case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36402 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-24 21:13:23 +00:00
..
CallingConvLower.cpp
DAGCombiner.cpp PR400 phase 2. Propagate attributed load/store information through DAGs. 2007-04-22 23:15:30 +00:00
LegalizeDAG.cpp Allow the lowering of ISD::GLOBAL_OFFSET_TABLE. 2007-04-20 23:02:39 +00:00
Makefile
ScheduleDAG.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSimple.cpp Removed tabs everywhere except autogenerated & external files. Add make 2007-04-16 18:10:23 +00:00
SelectionDAG.cpp PR400 phase 2. Propagate attributed load/store information through DAGs. 2007-04-22 23:15:30 +00:00
SelectionDAGISel.cpp Assertion when using a 1-element vector for an add operation. Get the 2007-04-24 21:13:23 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp fix a pasto 2007-04-18 03:01:40 +00:00