mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
2f69e4cf32
There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA).
This assert needs to addressed for post RA scheduler. Until that assert is addressed,
any passes that uses post ra scheduler will fail. So, I am temporarily disabling the
hexagon tests until that fix is in.
The assert is as follows:
assert(!MI->isTerminator() && !MI->isLabel() &&
"Cannot schedule terminators or labels!");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8
19 lines
473 B
LLVM
19 lines
473 B
LLVM
; RUN: true
|
|
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
|
; CHECK: combine(r{{[0-9]+}}, r{{[0-9]+}})
|
|
|
|
@j = external global i32
|
|
@k = external global i64
|
|
|
|
define void @foo() nounwind {
|
|
entry:
|
|
%0 = load i32* @j, align 4
|
|
%1 = load i64* @k, align 8
|
|
%conv = trunc i64 %1 to i32
|
|
%2 = call i64 @llvm.hexagon.A2.combinew(i32 %0, i32 %conv)
|
|
store i64 %2, i64* @k, align 8
|
|
ret void
|
|
}
|
|
|
|
declare i64 @llvm.hexagon.A2.combinew(i32, i32) nounwind readnone
|