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the simplification of frame index register scavenging to not have to check for available registers directly and instead just let scavengeRegister() handle it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107880 91177308-0d34-0410-b5e6-96231b3b80d8
385 lines
12 KiB
C++
385 lines
12 KiB
C++
//===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the machine register scavenger. It can provide
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// information, such as unused registers, at any point in a machine basic block.
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// It also provides a mechanism to make registers available by evicting them to
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// spill slots.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reg-scavenging"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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/// setUsed - Set the register and its sub-registers as being used.
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void RegScavenger::setUsed(unsigned Reg) {
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RegsAvailable.reset(Reg);
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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RegsAvailable.reset(SubReg);
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}
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bool RegScavenger::isAliasUsed(unsigned Reg) const {
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if (isUsed(Reg))
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return true;
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for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R)
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if (isUsed(*R))
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return true;
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return false;
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}
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void RegScavenger::initRegState() {
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ScavengedReg = 0;
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ScavengedRC = NULL;
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ScavengeRestore = NULL;
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// All registers started out unused.
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RegsAvailable.set();
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// Reserved registers are always used.
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RegsAvailable ^= ReservedRegs;
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if (!MBB)
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return;
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// Live-in registers are in use.
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for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
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E = MBB->livein_end(); I != E; ++I)
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setUsed(*I);
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// Pristine CSRs are also unavailable.
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BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB);
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for (int I = PR.find_first(); I>0; I = PR.find_next(I))
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setUsed(I);
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}
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void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
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MachineFunction &MF = *mbb->getParent();
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const TargetMachine &TM = MF.getTarget();
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TII = TM.getInstrInfo();
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TRI = TM.getRegisterInfo();
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MRI = &MF.getRegInfo();
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assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
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"Target changed?");
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// Self-initialize.
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if (!MBB) {
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NumPhysRegs = TRI->getNumRegs();
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RegsAvailable.resize(NumPhysRegs);
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// Create reserved registers bitvector.
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ReservedRegs = TRI->getReservedRegs(MF);
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// Create callee-saved registers bitvector.
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CalleeSavedRegs.resize(NumPhysRegs);
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const unsigned *CSRegs = TRI->getCalleeSavedRegs();
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if (CSRegs != NULL)
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for (unsigned i = 0; CSRegs[i]; ++i)
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CalleeSavedRegs.set(CSRegs[i]);
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}
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MBB = mbb;
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initRegState();
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Tracking = false;
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}
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void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
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BV.set(Reg);
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for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
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BV.set(*R);
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}
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void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) {
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BV.set(Reg);
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for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++)
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BV.set(*R);
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}
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void RegScavenger::forward() {
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// Move ptr forward.
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if (!Tracking) {
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MBBI = MBB->begin();
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Tracking = true;
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} else {
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assert(MBBI != MBB->end() && "Already at the end of the basic block!");
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MBBI = llvm::next(MBBI);
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}
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MachineInstr *MI = MBBI;
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if (MI == ScavengeRestore) {
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ScavengedReg = 0;
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ScavengedRC = NULL;
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ScavengeRestore = NULL;
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}
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if (MI->isDebugValue())
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return;
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// Find out which registers are early clobbered, killed, defined, and marked
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// def-dead in this instruction.
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// FIXME: The scavenger is not predication aware. If the instruction is
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// predicated, conservatively assume "kill" markers do not actually kill the
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// register. Similarly ignores "dead" markers.
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bool isPred = TII->isPredicated(MI);
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BitVector EarlyClobberRegs(NumPhysRegs);
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BitVector KillRegs(NumPhysRegs);
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BitVector DefRegs(NumPhysRegs);
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BitVector DeadRegs(NumPhysRegs);
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isUndef())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg || isReserved(Reg))
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continue;
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if (MO.isUse()) {
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// Two-address operands implicitly kill.
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if (!isPred && (MO.isKill() || MI->isRegTiedToDefOperand(i)))
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addRegWithSubRegs(KillRegs, Reg);
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} else {
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assert(MO.isDef());
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if (!isPred && MO.isDead())
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addRegWithSubRegs(DeadRegs, Reg);
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else
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addRegWithSubRegs(DefRegs, Reg);
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if (MO.isEarlyClobber())
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addRegWithAliases(EarlyClobberRegs, Reg);
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}
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}
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// Verify uses and defs.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isUndef())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg || isReserved(Reg))
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continue;
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if (MO.isUse()) {
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if (!isUsed(Reg)) {
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// Check if it's partial live: e.g.
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// D0 = insert_subreg D0<undef>, S0
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// ... D0
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// The problem is the insert_subreg could be eliminated. The use of
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// D0 is using a partially undef value. This is not *incorrect* since
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// S1 is can be freely clobbered.
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// Ideally we would like a way to model this, but leaving the
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// insert_subreg around causes both correctness and performance issues.
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bool SubUsed = false;
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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if (isUsed(SubReg)) {
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SubUsed = true;
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break;
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}
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assert(SubUsed && "Using an undefined register!");
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}
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assert((!EarlyClobberRegs.test(Reg) || MI->isRegTiedToDefOperand(i)) &&
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"Using an early clobbered register!");
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} else {
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assert(MO.isDef());
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#if 0
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// FIXME: Enable this once we've figured out how to correctly transfer
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// implicit kills during codegen passes like the coalescer.
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assert((KillRegs.test(Reg) || isUnused(Reg) ||
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isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
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"Re-defining a live register!");
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#endif
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}
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}
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// Commit the changes.
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setUnused(KillRegs);
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setUnused(DeadRegs);
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setUsed(DefRegs);
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}
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void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
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if (includeReserved)
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used = ~RegsAvailable;
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else
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used = ~RegsAvailable & ~ReservedRegs;
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}
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/// CreateRegClassMask - Set the bits that represent the registers in the
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/// TargetRegisterClass.
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static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
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for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
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++I)
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Mask.set(*I);
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}
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
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for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
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I != E; ++I)
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if (!isAliasUsed(*I))
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return *I;
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return 0;
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}
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/// getRegsAvailable - Return all available registers in the register class
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/// in Mask.
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void RegScavenger::getRegsAvailable(const TargetRegisterClass *RC,
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BitVector &Mask) {
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for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
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I != E; ++I)
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if (!isAliasUsed(*I))
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Mask.set(*I);
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}
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/// findSurvivorReg - Return the candidate register that is unused for the
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/// longest after StargMII. UseMI is set to the instruction where the search
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/// stopped.
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///
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/// No more than InstrLimit instructions are inspected.
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///
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unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
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BitVector &Candidates,
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unsigned InstrLimit,
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MachineBasicBlock::iterator &UseMI) {
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int Survivor = Candidates.find_first();
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assert(Survivor > 0 && "No candidates for scavenging");
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MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
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assert(StartMI != ME && "MI already at terminator");
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MachineBasicBlock::iterator RestorePointMI = StartMI;
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MachineBasicBlock::iterator MI = StartMI;
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bool inVirtLiveRange = false;
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for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
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if (MI->isDebugValue()) {
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++InstrLimit; // Don't count debug instructions
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continue;
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}
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bool isVirtKillInsn = false;
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bool isVirtDefInsn = false;
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// Remove any candidates touched by instruction.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isUndef() || !MO.getReg())
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continue;
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if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
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if (MO.isDef())
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isVirtDefInsn = true;
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else if (MO.isKill())
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isVirtKillInsn = true;
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continue;
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}
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Candidates.reset(MO.getReg());
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for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++)
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Candidates.reset(*R);
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}
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// If we're not in a virtual reg's live range, this is a valid
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// restore point.
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if (!inVirtLiveRange) RestorePointMI = MI;
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// Update whether we're in the live range of a virtual register
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if (isVirtKillInsn) inVirtLiveRange = false;
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if (isVirtDefInsn) inVirtLiveRange = true;
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// Was our survivor untouched by this instruction?
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if (Candidates.test(Survivor))
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continue;
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// All candidates gone?
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if (Candidates.none())
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break;
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Survivor = Candidates.find_first();
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}
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// If we ran off the end, that's where we want to restore.
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if (MI == ME) RestorePointMI = ME;
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assert (RestorePointMI != StartMI &&
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"No available scavenger restore location!");
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// We ran out of candidates, so stop the search.
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UseMI = RestorePointMI;
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return Survivor;
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}
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unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
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MachineBasicBlock::iterator I,
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int SPAdj) {
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// Mask off the registers which are not in the TargetRegisterClass.
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BitVector Candidates(NumPhysRegs, false);
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CreateRegClassMask(RC, Candidates);
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// Do not include reserved registers.
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Candidates ^= ReservedRegs & Candidates;
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// Exclude all the registers being used by the instruction.
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = I->getOperand(i);
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if (MO.isReg() && MO.getReg() != 0 &&
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!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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Candidates.reset(MO.getReg());
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}
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// Try to find a register that's unused if there is one, as then we won't
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// have to spill.
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if ((Candidates & RegsAvailable).any())
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Candidates &= RegsAvailable;
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// Find the register whose use is furthest away.
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MachineBasicBlock::iterator UseMI;
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unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
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// If we found an unused register there is no reason to spill it.
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if (!isAliasUsed(SReg))
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return SReg;
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assert(ScavengedReg == 0 &&
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"Scavenger slot is live, unable to scavenge another register!");
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// Avoid infinite regress
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ScavengedReg = SReg;
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// If the target knows how to save/restore the register, let it do so;
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// otherwise, use the emergency stack spill slot.
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if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
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// Spill the scavenged register before I.
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assert(ScavengingFrameIndex >= 0 &&
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"Cannot scavenge register without an emergency spill slot!");
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TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
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MachineBasicBlock::iterator II = prior(I);
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TRI->eliminateFrameIndex(II, SPAdj, NULL, this);
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// Restore the scavenged register before its use (or first terminator).
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TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
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II = prior(UseMI);
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TRI->eliminateFrameIndex(II, SPAdj, NULL, this);
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}
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ScavengeRestore = prior(UseMI);
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// Doing this here leads to infinite regress.
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// ScavengedReg = SReg;
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ScavengedRC = RC;
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return SReg;
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}
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