mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
0543dab791
Summary:
Two exceptions to this:
test/CodeGen/Mips/octeon.ll
test/CodeGen/Mips/octeon_popcnt.ll
these test extensions to MIPS64
One test is altered for MIPS-IV:
test/CodeGen/Mips/mips64countleading.ll
Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests
that dclo/dclz are not emitted.
Four tests fail and are not in this patch:
test/CodeGen/Mips/abicalls.ll
test/CodeGen/Mips/fcopysign-f32-f64.ll
test/CodeGen/Mips/fcopysign.ll
test/CodeGen/Mips/stack-alignment.ll
Depends on D3343
Reviewers: matheusalmeida, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3344
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206185 91177308-0d34-0410-b5e6-96231b3b80d8
243 lines
5.6 KiB
LLVM
243 lines
5.6 KiB
LLVM
; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=O32
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; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s -check-prefix=O32
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; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 < %s | FileCheck %s -check-prefix=N64
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; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=N64
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@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
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@i3 = common global i32* null, align 4
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; O32-DAG: lw $[[R0:[0-9]+]], %got(i3)
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; O32-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)
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; O32: movn $[[R0]], $[[R1]], ${{[0-9]+}}
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; N64-DAG: ldr $[[R0:[0-9]+]]
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; N64-DAG: ld $[[R1:[0-9]+]], %got_disp(i1)
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; N64: movn $[[R0]], $[[R1]], ${{[0-9]+}}
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define i32* @cmov1(i32 %s) nounwind readonly {
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entry:
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%tobool = icmp ne i32 %s, 0
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%tmp1 = load i32** @i3, align 4
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%cond = select i1 %tobool, i32* getelementptr inbounds ([3 x i32]* @i1, i32 0, i32 0), i32* %tmp1
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ret i32* %cond
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}
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@c = global i32 1, align 4
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@d = global i32 0, align 4
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; O32-LABEL: cmov2:
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; O32: addiu $[[R1:[0-9]+]], ${{[a-z0-9]+}}, %got(d)
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; O32: addiu $[[R0:[0-9]+]], ${{[a-z0-9]+}}, %got(c)
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; O32: movn $[[R1]], $[[R0]], ${{[0-9]+}}
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; N64-LABEL: cmov2:
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; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
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; N64: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
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; N64: movn $[[R1]], $[[R0]], ${{[0-9]+}}
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define i32 @cmov2(i32 %s) nounwind readonly {
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entry:
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%tobool = icmp ne i32 %s, 0
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%tmp1 = load i32* @c, align 4
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%tmp2 = load i32* @d, align 4
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%cond = select i1 %tobool, i32 %tmp1, i32 %tmp2
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ret i32 %cond
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}
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; O32-LABEL: cmov3:
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; O32: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone {
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entry:
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%cmp = icmp eq i32 %a, 234
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%cond = select i1 %cmp, i32 %b, i32 %c
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ret i32 %cond
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}
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; N64-LABEL: cmov4:
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; N64: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
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; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone {
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entry:
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%cmp = icmp eq i32 %a, 234
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%cond = select i1 %cmp, i64 %b, i64 %c
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ret i64 %cond
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}
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; slti and conditional move.
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;
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; Check that, pattern
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; (select (setgt a, N), t, f)
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; turns into
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; (movz t, (setlt a, N + 1), f)
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; if N + 1 fits in 16-bit.
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; O32-LABEL: slti0:
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; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @slti0(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, 32766
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%cond = select i1 %cmp, i32 3, i32 5
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ret i32 %cond
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}
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; O32-LABEL: slti1:
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; O32: slt ${{[0-9]+}}
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define i32 @slti1(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, 32767
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%cond = select i1 %cmp, i32 3, i32 5
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ret i32 %cond
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}
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; O32-LABEL: slti2:
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; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @slti2(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, -32769
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%cond = select i1 %cmp, i32 3, i32 5
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ret i32 %cond
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}
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; O32-LABEL: slti3:
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; O32: slt ${{[0-9]+}}
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define i32 @slti3(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, -32770
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%cond = select i1 %cmp, i32 3, i32 5
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ret i32 %cond
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}
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; 64-bit patterns.
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; N64-LABEL: slti64_0:
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; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
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; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i64 @slti64_0(i64 %a) {
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entry:
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%cmp = icmp sgt i64 %a, 32766
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%conv = select i1 %cmp, i64 3, i64 4
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ret i64 %conv
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}
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; N64-LABEL: slti64_1:
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; N64: slt ${{[0-9]+}}
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define i64 @slti64_1(i64 %a) {
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entry:
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%cmp = icmp sgt i64 %a, 32767
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%conv = select i1 %cmp, i64 3, i64 4
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ret i64 %conv
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}
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; N64-LABEL: slti64_2:
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; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
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; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i64 @slti64_2(i64 %a) {
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entry:
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%cmp = icmp sgt i64 %a, -32769
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%conv = select i1 %cmp, i64 3, i64 4
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ret i64 %conv
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}
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; N64-LABEL: slti64_3:
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; N64: slt ${{[0-9]+}}
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define i64 @slti64_3(i64 %a) {
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entry:
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%cmp = icmp sgt i64 %a, -32770
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%conv = select i1 %cmp, i64 3, i64 4
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ret i64 %conv
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}
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; sltiu instructions.
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; O32-LABEL: sltiu0:
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; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @sltiu0(i32 %a) {
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entry:
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%cmp = icmp ugt i32 %a, 32766
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%cond = select i1 %cmp, i32 3, i32 5
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ret i32 %cond
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}
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; O32-LABEL: sltiu1:
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; O32: sltu ${{[0-9]+}}
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define i32 @sltiu1(i32 %a) {
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entry:
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%cmp = icmp ugt i32 %a, 32767
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%cond = select i1 %cmp, i32 3, i32 5
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ret i32 %cond
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}
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; O32-LABEL: sltiu2:
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; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @sltiu2(i32 %a) {
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entry:
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%cmp = icmp ugt i32 %a, -32769
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%cond = select i1 %cmp, i32 3, i32 5
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ret i32 %cond
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}
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; O32-LABEL: sltiu3:
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; O32: sltu ${{[0-9]+}}
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define i32 @sltiu3(i32 %a) {
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entry:
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%cmp = icmp ugt i32 %a, -32770
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%cond = select i1 %cmp, i32 3, i32 5
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ret i32 %cond
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}
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; Check if
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; (select (setxx a, N), x, x-1) or
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; (select (setxx a, N), x-1, x)
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; doesn't generate conditional moves
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; for constant operands whose difference is |1|
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define i32 @slti4(i32 %a) nounwind readnone {
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%1 = icmp slt i32 %a, 7
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%2 = select i1 %1, i32 4, i32 3
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ret i32 %2
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}
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; O32-LABEL: slti4:
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; O32-DAG: slti [[R1:\$[0-9]+]], $4, 7
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; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], 3
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; O32-NOT: movn
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; O32:.size slti4
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define i32 @slti5(i32 %a) nounwind readnone {
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%1 = icmp slt i32 %a, 7
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%2 = select i1 %1, i32 -3, i32 -4
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ret i32 %2
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}
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; O32-LABEL: slti5:
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; O32-DAG: slti [[R1:\$[0-9]+]], $4, 7
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; O32-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4
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; O32-NOT: movn
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; O32:.size slti5
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define i32 @slti6(i32 %a) nounwind readnone {
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%1 = icmp slt i32 %a, 7
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%2 = select i1 %1, i32 3, i32 4
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ret i32 %2
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}
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; O32-LABEL: slti6:
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; O32-DAG: slti [[R1:\$[0-9]+]], $4, 7
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; O32-DAG: xori [[R1]], [[R1]], 1
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; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], 3
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; O32-NOT: movn
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; O32:.size slti6
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