Andrew Trick 0701564377 Mark the x86 machine model as incomplete. PR17367. ... Ideally, the machinel model is added at the time the instructions are defined. But many instructions in X86InstrSSE.td still need a model. Without this workaround the scheduler asserts because x86 already has itinerary classes for these instructions, indicating they should be modeled by the scheduler. Since we use the new machine model for other instructions, it expects a new machine model for these too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191391 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-25 18:14:12 +00:00
..
AsmMatcherEmitter.cpp
AsmWriterEmitter.cpp
AsmWriterInst.cpp
AsmWriterInst.h
CallingConvEmitter.cpp
CMakeLists.txt
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp
CodeGenDAGPatterns.h
CodeGenInstruction.cpp
CodeGenInstruction.h
CodeGenIntrinsics.h
CodeGenMapTable.cpp
CodeGenRegisters.cpp
CodeGenRegisters.h
CodeGenSchedule.cpp
CodeGenSchedule.h
CodeGenTarget.cpp
CodeGenTarget.h
CTagsEmitter.cpp
DAGISelEmitter.cpp
DAGISelMatcher.cpp
DAGISelMatcher.h
DAGISelMatcherEmitter.cpp
DAGISelMatcherGen.cpp
DAGISelMatcherOpt.cpp
DFAPacketizerEmitter.cpp
DisassemblerEmitter.cpp
FastISelEmitter.cpp
FixedLenDecoderEmitter.cpp
InstrInfoEmitter.cpp
IntrinsicEmitter.cpp
LLVMBuild.txt
Makefile
OptParserEmitter.cpp
PseudoLoweringEmitter.cpp
RegisterInfoEmitter.cpp
SequenceToOffsetTable.h
SetTheory.cpp
SetTheory.h
SubtargetEmitter.cpp	Mark the x86 machine model as incomplete. PR17367.	2013-09-25 18:14:12 +00:00
TableGen.cpp
TableGenBackends.h
tdtags
TGValueTypes.cpp
X86DisassemblerShared.h
X86DisassemblerTables.cpp
X86DisassemblerTables.h
X86ModRMFilters.cpp
X86ModRMFilters.h
X86RecognizableInstr.cpp
X86RecognizableInstr.h